A Cache System Design for CMPs with Built-In Coherence Verification

Chang, C. P. (2009). A Cache Management Scheme for Pattern-Matching Localization at the Client Side [master's thesis, National Chiao Tung University]. Airiti Library. https://doi.org/10.6842/NCTU.2009.00769
Ho, H. Y. (2017). An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-0401201815551625
Chen, H. C. (2005). Designs of High-Performance and Low-Power Cache Architectures [doctoral dissertation, Tamkang University]. Airiti Library. https://doi.org/10.6846/TKU.2005.00420
Chang, S. F. (2004). The Design and Implementation of a cache within fast switch controller chip [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2004.01200
Fu, C. Y. (2010). A Shared-Variable Based Synchronization Approach to Efficient Cache Coherence Simulations for Multi-Core Systems [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-1901201111412896