低電壓CMOS鎖相迴路於脈波產生器之設計研究

本論文的主要目標在於設計一應用於脈波產生器之低電壓CMOS鎖相迴路(Low Voltage CMOS Phase Locked Loops)。此電路主要是利用電荷充電泵之核心概念設計，其關鍵電路方塊由相頻偵測器(Phase Frequency Detector)、電荷充電泵(Charge Pump)、壓控振盪器(Voltage Controlled Oscillator)、迴路濾波器(Loop Filter)，及除頻器(Divider)所組成。為提高鎖相迴路抗雜訊及對溫度穩定之性能需求，本論文提出以下的方式：首先，相頻偵測器是採用可消除Dead-Zone雜訊影響的Pre-Charge架構來實現，電荷充電泵所使用的定電流源為可對溫度作補償的熱電壓參考電路，另外在數位雜訊的避免上也使用了非重疊電路作補償，壓控振盪器的部分使用了環振盪器(Ring Oscillator)，每一級皆使用差分輸入及差分輸出的放大器以避免抖動雜訊的發生，在迴路濾波器的部分，利用二階的系統將相頻偵測器與電荷充電泵所產生的高頻雜訊濾除，同時降低電壓跳動對壓控振盪器的影響，此時整個系統將變為三階的系統，需考量其穩定度。本研究採用並聯電容值之調整以求穩定度及相位的邊界(Phase Margin)，除頻器除了有除頻的功用之外同時可作為輸出的緩衝器。本文所設計之鎖相迴路採用台灣積體電路製造公司(TSMC) 0.35μm 1P4M製程來實現，佈局面積為300μm*700μm，其規格為輸入6M Hz，輸出為12M Hz、24M Hz、48M Hz、96M Hz四個輸出，其壓控振盪器最大頻率為125M Hz，我們量測其抖動在6M Hz的輸出頻率時為720ps，供應電壓為2.7V ~ 3.3V，最大功率消耗為10mW。本論文所設計之鎖相迴路依照其特性可使用於脈波產生器及頻率合成器之應用。

關鍵字

除頻器；迴路濾波器；壓控振盪器；鎖相迴路；環振盪器；相頻偵測器；電荷充電泵

並列摘要

The aim of this thesis is to design a low voltage CMOS phase locked loop (PLL) for clock generator applications. The charge pump concept has been used in the PLL implementation and the core circuit blocks of the system consist of a phase frequency detector, charge pump, voltage controlled oscillator, loop filter and divider. This thesis adopts some methods below in order to improve the noise and stability performance of the PLL. Firstly, the frame of pre-charge stage is used to eliminate the noise of dead-zone in phase frequency detector. Secondly, the VT reference circuit has been used to design constant current source in charge pump for temperature compensation, and the non-overlapping circuit is used to reduce the digital noise from the timing mismatch. The ring oscillator using fully differential input and output stage in voltage controlled oscillator prevents the jitter noise from the power line and substrate. Finally, we use the second order loop filter to decrease the influence of voltage step and filter out the higher frequency noise from phase frequency detector and charge pump. The magnitude changing of parallel capacitor is used for obtaining enough phase margins. The divider provides both functions on frequency division and the output buffer for phase locked loop. The chip has been implemented in the TSMC 0.35μm 1P4M CMOS technology and the core layout area is 300μm * 700μm. For 2.7 to 3.3V power supply, the input frequency is 6 M Hz, and the output frequencies are 12 M Hz, 24M Hz, 48M Hz, and 96M Hz. The results show the jitter is 720ps at 6 MHz and the maximum power consumption is 10mW at 3V power supply. The proposed PLL has been shown its performance can be used in clock generator and frequency synthesizer applications.

並列關鍵字

phase frequency detector ； charge pump ； Phase locked loops ； loop filter ； divider and ring oscillator

參考文獻

[2] Behzad Razavi,”Design of Monolithic Phase-Locked Loops and Clock Recovery Circuit –A Tutorial”, Monolithic Phase-Locked Loops and Recovery Circuit, A Select Reprint Volume IEEE Solid-State Circuit Council, Sponsor, 1996

[5] Ian A. Young,and Jeffrey K. Greason, and Keng L. Wong, “A PLL Clock Generator with 5 to 100M Hz of Lock Range for Microprocessor”, IEEE Journal of Solid State Circuit, Vol. SC-27, No.11, pp.1599-1607, November 1992

[8] Avner Efendovich, Yachin Afek, Coby Sella and Zeev Bikowsky, “ Multi-Frequency Zero-Jitter Delay-Locked Loop “, IEEE 1993 Custom Integrated Circuit Conference

[9] Mark Van Paemel, “Analysis of a Charge-Pump PLL: A New Model”, IEEE Transaction On Communication, Vol. 42, No. 6, pp. 2490-2498, July 1994

[13] National Semiconductor, PLL Made Easier version 1.6 Online Help, National Semiconductor, March 1999

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低電壓CMOS鎖相迴路於脈波產生器之設計研究

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