全差動取樣保持積體電路之設計研究

Research of the Fully Differential Sample and Hold Integrated Circuit Design

鄭錦鐘(chin-chung cheng)

指導教授 ： 鍾文耀

中原大學/工學院/電子工程研究所/碩士(2001年)

https://doi.org/10.6840/cycu200100285

摘要

本論文主要目的在設計一應用於類比至數位轉換器(A/D Converter)前端之全差動取樣保持積體電路(Fully Differential Sample and Hold Integrated Circuit)。此電路主要是利用相關雙重取樣(Correlated Double Sampling)之概念設計，其能有效降低運算放大器有限增益、輸入偏移電壓與低頻雜訊所產生的解析度誤差，而在非重疊時脈產生器的延遲相位控制與全差動架構下，可消除取樣抖動與電荷注入效應。取樣保持電路中的運算放大器，則採用摺疊式疊接架構，在4pF的負載電容下，可以得到210MHz的單位增益頻寬並維持相位邊限在65o，且其低頻增益為67db，而採用交換電容緩衝組態方
式模擬其變動率與穩定時間分別為190mV/ns及15ns。
本文所設計的取樣保持電路是採用台灣積體電路製造公司(TSMC)所提供的0.35uM 1P4M CMOS製程來實現，佈局面積為1475.8*1481.8μm2。晶片量測結果，在輸入電壓為-2V ~ +2V，取樣基底為-5mV ~ +14mV。操作電源電壓為3.3V時，功率消耗小於33.76mW。本論文所
計之取樣保持電路可作為類比至數位轉換器之前端電路。

關鍵字

取樣基底 ； 摺疊式疊接放大器 ； 全差動取樣保持電路 ； 相關雙重取樣

並列摘要

The major objective of this thesis is to design and implement a fully differential sample and hold circuitry. The correlated double sampling (CDS) technique is used in this circuit design. Moreover, the core circuit of the design is fully differential folded cascode amplifier.
The architecture of CDS technique can minimize error due to finite offset error, 1/f noise, and finite opamp gain. Further, use the phase delay control and fully differential architecture can eliminate aperture jitter and charge injection. The results of HSPICE simulation show that the fully differential opamp has 67dB DC gain, and the unity gain frequency of the amplifier is 210MHz.
The proposed sample and hold circuit has been fabricated with TSMC .35μm 1P4M CMOS technology and the chip area is 1475.8*1481.8μm2 .The measured result shows that the sample pedestal is –5mV~ +14mV, input voltage range is –2V~ +2V, and the power consumption is 33.76mW from a single 3.3V supply.

並列關鍵字

sample pedestal ； correlated double sampling ； fully differential folded cascode amplifier ； fully differential sample and hold

參考文獻

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