透過您的圖書館登入
IP:18.221.53.209
  • 學位論文

以田口方法改善金線偏移之銲線製程問題

Research for Wire Sweep on IC Package Using Taguchi Methods

指導教授 : 鍾文仁
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


現今IC的發展趨勢是朝著快速、多功能、高I/O數的方向發展,而當IC元件朝向薄型元件與高密度發展時,金線偏移將是微電子構裝在轉移成型製程中最主要的缺陷之一。故金線偏移分析的探討亦將變得更困難且具挑戰性。 本文針對BGA 208L之封裝成型製程作研究,即依據實務經驗選出影響金線偏移的主要製程參數,接著依此主要製程參數給予適當的因素水準去從事封裝成型,再由x-ray量測各個製程條件下的金線偏移量,最後利用田口方法來尋求最佳的製程參數組合,以減低封裝時的金線偏移。

並列摘要


The development trend of IC is high speed, good electronic performance, and high I/O interconnection. As thinner and denser IC packages coming, wire sweep has become one of the major defects in the encapsulation of microelectronic chips by the transfer molding process. So wire-sweep analysis becomes more challenging and troublesome. This paper presents the study for the transfer molding process of BGA 208L. It is according to the actual situation experience to select the main process parameter that influence the wire-sweep. And give some suitable process condition to package, and then the x-ray is used to Measurement the wire-sweep of different process parameters. In addition, the Taguchi method is used to find optimal processing conditions to reduce the wire-sweep problems.

參考文獻


Encapsulation in of Semiconductor Chips Using
6.C. H. Chang "Mold-Flow Analysis of High-Density
IC Encapsulation" Master
Thesis Chung Yuan Christian University July
Moldflow Corporation New York 2003.

被引用紀錄


吳丘文(2012)。電漿清潔對CMOS封裝銲線強度改善研究〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://doi.org/10.6841/NTUT.2012.00223
林錫慶(2010)。運用田口方法探討浮凸螺帽焊接之最佳化〔碩士論文,國立臺北科技大學〕。華藝線上圖書館。https://doi.org/10.6841/NTUT.2010.00533
沈寶明(2014)。利用福特8D手法改善晶圓測試機台誤判率〔碩士論文,中原大學〕。華藝線上圖書館。https://doi.org/10.6840/cycu201400740
蘇家慶(2011)。彩色濾光片PS/RGB製程膜厚預測實驗計畫法之規則建立〔碩士論文,中原大學〕。華藝線上圖書館。https://doi.org/10.6840/cycu201100767
王沛晴(2011)。垂直軸風力發電機葉片最佳設計因子探討之研究 —以Savonius風車為例—〔碩士論文,中原大學〕。華藝線上圖書館。https://doi.org/10.6840/cycu201100659

延伸閱讀