由於可攜式產品的普及,非揮發性記憶體在半導體記憶元件中所扮 演的角色愈來愈重要。隨著半導體製程技術的精進,半導體非揮發性記 憶體亦逐年在進步。然而,隨著元件的微縮,具功率消耗低、元件密度 高、操作速度快、且相容於CMOS 製程等特色的記憶元件將是未來發展 的趨勢。 本論文以熱電洞注入對非重疊佈值記憶元件之可靠度研究之分析做 為研究主題,此記憶元件的抹除係利用帶對帶穿遂效應引發熱電洞的注 入,並以場效電晶體退化模型為理論基礎推算熱電洞對介面狀態的變化 率。並藉由兩個實驗去驗證其模型的準確性,觀察不同的閘極與汲極偏 壓對元件進行抹除之操作之影響,經由詳細的實驗量測,配合理論推算 及元件模擬的相互比對,可成功計算出其介面狀態密度變化率,並確認 該元件模型的準確性。
Non-volatile memories play more and more important roles with the emergence of the portable microelectronic products. The non-volatile semiconductor memories have rapidly progressed as the semiconductor technologies advance. The memory devices having low power consumption, high density, high-speed operation, and full compatibility with the standard CMOS processing will be the future development trend in non-volatile memories. This work explores the erasing charge injection in Non-overlapped Implantation (NOI) MOSFETs. The erasing chracteristics of the NOI nMOSFETs are studied in terms of band-to-band induced hot hole injection and interface trap generation. Two experiments are designed to verify the generation model accuracy, and erase operation influence under difference drain and gate biases of the NOI device. It has been successful to confirm the hot-hole-induced interface trap generation by cross examination between these two experiments, including device simulation and theoretical deduction.