本論文探討多種基於速寫演算法的流量計數方式,以實際的核心網路流量來模擬測試並比較其效能。將兩種演算法CM-Sketch(Count Min Sketch)與MPC(Multiple Probabilistic Counting),以硬體描述語言(Verilog HDL)實現在NetFPGA-10G開發平台,並且完成具有網路資料分流(Network Traffic Tap)功能之高速網路流量量測系統。此系統,在觀測時間之內,可以量測流經觀測點所有不同種類封包流的個數(Distinct Flow Count),以及每一個流量中的封包出現次數。
Network traffic flow measurement and analysis are the essential part of the network intrusion detection system design. In this dissertation, we study selected sketch-based algorithms which are capable of estimating the cardinality and multiplicities of traffic flow in high-speed core networks. We explore these algorithms with real-world network traffic traces and implement two of them in NetFGPA 10G platform. The traffic measurement prototype is capable of acting as a network tap to identify the number of distinct IP flows and the number of times a packet belongs to a particular IP flow. We also provide register interfaces for the host to retrieve these measurement results for high level application design.