在本篇論文中,我們使用NetFPGA發展平台,以硬體描述語言Verilog HDL,實現了以速寫演算法為基礎的流量變異偵測之硬體系統。並且詳述硬體系統之FPGA設計與開發流程,我們更討論本系統之關鍵模組,如速寫演算法模組,所需的雜湊函數與記憶體空間之硬體資源與效能間之取捨,來達成高速(4Gbps)即時流量變異偵測之目標。
In this thesis, we implement a sketch-based network traffic change detection system on NetFPGA.The architecture and FPGA flow on several key modules are presented in detail. We further explore the hardware resources with trade-offs to achieve on-line, wire-speed (4Gbps) network traffic change detection.