摘要
如今，時序差異排序已成為改善電路效能的有效方法。但由於循序電路中競跑效應所造成的限制，單由時序差異排序所得到的最小時鐘週期，並無法達到循序電路最佳化的最低下限值。在本篇論文當中，我們提出兩種新的考慮競跑效應的時序差異排序演算法。首先，我們說明DIANA演算法，DIANA演算法站在插入訊號延遲的觀點來進行時序差異排序。在此演算法中，插入訊號延遲的數量值必須被適當的加以調整(因而花費較多運算時間)，否則插入訊號延遲有可能影響到電路中的就序時間限制(Setup Constraint)。因此，我們提出一種更有效率的RCA演算法，RCA演算法站在調整時序限制(Clocking Constraints)的角度來改善時序差異排序。在時鐘週期最小化的反覆運算過程中，有效地放鬆(Relax)限制電路效能的保持時間限制(Hold Constraint)。本篇論文所要達到的目標，不僅是要達到最小化時鐘週期，更要降低所需插入訊號延遲的數量值。實驗過程與結果皆印證我們的演算法可以得到循序電路最佳化的最低下限值以及較少的插入訊號延遲。此外，我們也成功將此演算法應用在其他循序電路最佳化的方法之上。
並列摘要
It is well known that the clock skew can be exploited as a manageable resource to improve the circuit performance. However, due to the limitation of race conditions, the min-period clock skew scheduling often does not achieve the lower bound of sequential timing optimization. In this thesis, two new clock skew scheduling algorithms are proposed to determine clock skew schedule by taking race conditions into account. First, we present the delay insertion and non-zero skew algorithm (DIANA), which stands from the viewpoint of delay insertion. Since delay insertion may influence setup constraints, the amount of delay insertion should be properly controlled. Second, we present a more efficient algorithm, called race-condition-aware (RCA) algorithm, which stands from the viewpoint of clocking constraints. The hold constraints that actually limit circuit performance are deleted during the iteration process for clock period reduction. The clock period can be further optimized without over-relaxing the hold constraints. Our objective is not only to optimize the clock period, but also to minimize heuristically the required inserted delay. Experiments with benchmark circuits consistently demonstrate that our approach achieves the lower bound of sequential timing optimization. In addition, we have generalized our approach to other sequential timing optimization techniques.