- 學位論文
CMOS元件庫設計最佳化方法於時序效應之研究
The Study of Timing Effects on CMOS Cell Library Design Optimization
摘要
現在被廣泛應用於產業界之數位和類比混合模式的晶片都採用CMOS製程技術來達成。在幾年以前，產業界大量投入類比電路研發設計而作成智財權(IP, Intellectual Property)，如A/D轉換器、D/A轉換器、LDO…等等[1]。為提高類比電路設計最佳化而延伸出類比佈局設計方法與演算法[3]，使類比電路佔約60%的晶片面積。隨著環保綠能與多功能之需求，製程技術不斷朝向微小化演進，各種電路設計將朝向低電壓、低功率消耗且越多功能的整合電路研發設計，將類比電路面積縮小到佔15%~20%的晶片面積左右，大部分面積將會是數位化電路。數位電路因為電路複雜且龐大且佔面積比例升高。為了達到time to market，通常會採用自動化佈局工具(APR, Auto Place and Routing)來完成數位部分或是整個晶片之佈局。而標準元件庫關係到晶片的效能、功率消耗以及頻率。 本論文結合了製程參數、電學原理、電路合成、自動化佈局、完全手動佈局設計和驗證演算法設計出一套新的電路設計方法，此新的電路設計方法稱之為預先整合製程技術、電路合成、自動化佈局、手動佈局和驗證之CMOS新電路設計方法("The New Method Of CMOS Circuit Design With Pre-Integrated Fabrication, Circuit-Synthesis, A.P.R., Fully Layout And Verification", PIFSALV)。可以應用於各種製程技術的電路元件庫設計與建立。本研究論文使用CMOS 0.35um 製程技術，將標準元件庫之設計預先整合製程技術、電學原理、電路合成、自動化佈局、完全手動佈局設計和驗證演算法。將晶片的面積與電氣特性予以最佳化，並且提高可靠度，建構完整的積體電路研發設計與驗證環境。 在未來，可利用此元件庫採用APR或是Fully Layout作成單晶片，以此研究論文提出的新設計方法去設計A/D轉換器、D/A轉換器,ROM,RAM和其他應用電路作成-ASIC IC或是IP，發展成一系列應用晶片,可加入其他應用電路廣泛應用於生物醫學和其他工商業用途，例如血糖測試器,消費性產品….等等。
並列摘要
It is currently widely used in industry. A digital and analog mixed-mode chip is using CMOS technology to achieve. In a few years ago, a large number of industry to invest R & D design of analog circuits and made the IP (Intellectual Property), such as A / D converter, D / A converter, the LDO ... [1]. For analog circuit design optimization and extension of analog layout design methods and algorithms [3], the analog circuits accounted for approximately 60% of chip area. With the green environmental protection with a multi-functional demand, process technology continuously towards the evolution of miniaturization, a variety of circuit design will be toward the low-voltage, low power consumption and more multi-functional R & D and design of integrated circuits, analog circuits reduce the area to 15% ~ about 20% of chip area, most of the area will be digitized circuit. Digital circuits because of circuit complexity and the large and accounted for area ratio increased. In order to achieve the time to market usually using the APR (Auto Place and Routing) to complete the layout of the digital part or the entire chip. The standard cell libraries related to the performance of the chip, power consumption and frequency. This thesis is a combination of process parameters, electrical principles, automated layout, completely manual layout design and verification algorithms to design a new set of circuit design, this new circuit design method called pre-integration process, circuit synthesis, automated layout completely manual layout, verify CMOS circuit design method ("The New Method Of CMOS Circuit Design With the Pre-Integrated Fabrication, Circuit-Synthesis, APR Fully the Layout And Verification" PIFSALV). It can be applied to a variety of process technologies, circuit library design and build. This research paper using the CMOS 0.35um process technology, the design of standard cell libraries pre-integrated process technology, electrical principles, circuit synthesis, A.P.R., fully layout and verification algorithms. The chip area and the electrical characteristics to be optimized, and to increase reliability, and construct a complete integrated circuit R & D design and verification environment. In the future, you can use this library to APR or Fully the Layout made single-chip, this research paper presents a new design method to design the A / D converter, D / A converter, ROM, RAM, and other application circuit made - ASIC IC or IP, to develop into a range of applications chip can be added to the other application circuits are widely used in biomedical and other industrial and commercial uses, such as blood sugar tester, consumer products ....