摘要
在同步循序電路中，時鐘樹的工作是使得電路中所有正反器能夠同步。因此，如何在時鐘樹合成階段使得時鐘樹的時序差異最小化，是一項非常重要的工作，而負載相配的技術是降低時序差異常用的方法之一。另一方面，如何分佈時鐘訊號使得電路有較低的功率也是另一個重要的問題，時鐘閘控制技術是公認可以有效降低功率消耗的技術之一。然而由於使用時鐘閘控制這種設計樣式，使得時鐘樹可能會包含不同型態的邏輯閘，例如，AND 閘、OR 閘和時序緩衝器，如果位在同一層的邏輯閘，其型態不相同，則意味者他們會有不同的時序行為，則負載相配的方法變得沒有辦法去控制時序差異。根據這些觀察，本篇論文提出了一個新的零時序差異時鐘閘控制時鐘樹合成方法。透過結合負載相配的方法，我們的方法可以有效地降低時鐘閘控制時鐘樹的時序差異。跟目前工業界常用的合成工具作比較後發現，實驗結果顯示我們的方法在每個不同的製程邊界皆可以有效的降低時序差異，且只有稍許的損失在時鐘樹面積及時鐘樹功率消耗方面。
並列摘要
In synchronous sequential circuits, clock tree is used for synchronizing all flip-flops in a chip. Thus, clock skew minimization is very important in the clock tree synthesis. The load-matching technique has been recognized as one of the most effective techniques to reduce the clock skew. On the other hand, it is also important to distribute the clock signal with low power. Clock gating has been recognized as one of the most effective techniques to reduce the power consumption. However, due to clock gating design style, the clock tree may include different types of logic gates, e.g., AND gates, OR gates, and buffer gates. If the logic gates at the same level are in different types, which have different timing behaviors, the load-matching technique cannot control the clock skew. Based on that observation, in this thesis, we present a new zero skew gated clock tree synthesis approach. By combining load-matching technique, our approach can greatly reduce clock skew of gated clock tree. Compared with the industry-strength gated clock tree synthesis, experimental data show that our approach can significantly reduce the clock skew in every process corner with a small penalty on the clock tree area and the clock tree power consumption.