Clock Tree Optimization for the Tolerance of Process Variation

具製程變異容忍度之時鐘樹最佳化

黃世旭(Shih-Hsu Huang) ； 聶佑庭(Yow-Tyng Nieh) ； 呂逢彬(Feng-Pin Lu)

《中原學報》 33卷3期 (2005/09) Pp. 513-518

https://doi.org/10.6358/JCYU.200509.0513

摘要

隨著製程技術縮小至深次微米，製程變異容忍度在時鐘樹設計上已成為一個重要的課題。商用佈局軟體的目標，往往是零時序差異或有限的時序差異。然而，事實上，零時序差異或者是最小時序差異演算法所得到的時鐘樹，其時序對製程變異非常敏感。在本篇論文中，我們研究有關於製程變異容忍度的時鐘樹最佳化方法。我們的基本想法，是利用可允許的時序差異值來提高電路的時序可靠度。在製程變異上面，每個時鐘緩衝器的延遲值被表示為一個範圍值。我們最佳化的目的，不僅是要最大化製程變異容忍度，並且要最小化整個電路時鐘緩衝器的總面積。實驗結果一致顯示，我們的方法對於商用軟體所合成的時鐘樹可以有很大的改善。

關鍵字

時鐘樹 ； 製程變異 ； 可用時序差異 ； 時序可靠度 ； 時序差異排序

並列摘要

As manufacturing technology shrinks to the deep submicron process, the tolerance of process variation becomes an important subject in the clock tree design. The objective of commercially available layout tools is often zero skew or a fixed skew bound. However, in fact, zero skew or minimal skew approaches may be sensitive to process variations. In this paper, we study the clock tree optimization for the tolerance of process variation. Our basic idea is to make use of the permissible clock skew to enhance the timing reliability of a circuit. Due to the concern of process variation, the delay of each clock buffer is treated as a range instead of a single value. Our optimization goal is not only to maximize the tolerance of the circuit to process variation, but also to minimize the total area of clock buffers. Benchmark data consistently show that our approach achieves very good results.

並列關鍵字

Clock Tree ； Process Variation ； Useful Skew ； Timing Reliability and Clock Schedule