平面規劃階段之雙重電壓源元件置換及 電壓島建構改善

Dual Supply Voltage Scaling and Voltage Island Construction Refinement at Floorplan Stage

徐文俊(WEN-CHUN HSU)

指導教授 ： 陳美麗

中原大學/工學院/資訊工程研究所/碩士(2008年)

https://doi.org/10.6840/cycu200900591

摘要

隨著IC 製程技術不斷進步，IC 產業在進入深次微米(Deep
Submicron)的時代後，市場需求的可攜式電子產品功能越來越複雜，
尺寸亦越來越小，然而，IC 晶片上的功率消耗卻會越來越大。因此，
在現代的晶片設計中，如何降低晶片的功率消耗並且維持原有晶片的
效能，成為一個相當重要的議題。雙重電壓源設計能夠在滿足電路的
時序之下，有效率地降低晶片的功率消耗。本論文使用雙重電壓源設
計，提出ㄧ個在平面規劃階段配派標準元件工作電壓並接著規劃出高
低電壓島區域的演算法，降低晶片整體功率消耗以及電壓網路資源
(Power-Network Resource)的需求量。
本論文提出之演算法可分為四個步驟：(一)分析電路並依據連線關
係及slack 值來群組化標準元件，接著以電路中違反時序限制的標準
元件個數及電路佈局中未使用到的面積(White Space)做為考量，對標
準元件群組做平面規劃；(二)將slack 為負之標準元件配派為高電壓
以修正時序錯誤，並在符合電路時序限制之下，對所有高電壓標準元
件重新配派工作電壓，改善功率消耗；(三) 在符合時序限制之下，將
ㄧ包含低工作電壓標準元件以及高工作電壓標準元件的標準元件群
組，分割成ㄧ高工作電壓群組及一低工作電壓群組；(四)以電壓網路
資源(Power-Network Resource)的需求量及電路佈局中未使用到的面
積(White Space)為考量，改善平面規劃。
從實驗結果可以看出，在ISCAS 的四個測試電路上，本論文能夠
有效的減少電路的功率消耗及電壓源網路資源的需求，平均能夠達到
50.52%的功率消耗改善並且減少27.90%的電壓源網路資源的需求，
另外，電路佈局中未使用到的面積(White Space)平均為電路佈局總面
積的3.58%。

關鍵字

電壓網路資源 ； 電壓島區域 ； 平面規劃階段 ； 雙重電壓源設計

並列摘要

With the improvement in the IC process technology, after IC Industry
enters the Deep Submicron era, the function of portable electronic
products is getting more complex, and the size is getting smaller with
increasing in power consumption. Therefore, it’s a very important issue to
reduce the power consumption of the chips and keep original
performance of the chips in the modern VLSI designs. Using dual supply
voltages on VLSI designs is an efficient method to reduce power
consumption and maintain the circuit performance. In this paper, we
propose a voltage scaling method, and then generate high or low voltage
island in the floorplanning stage to reduce power consumption and the
requirement of power-network resource by using dual supply voltage.
Our algorithm includes the following four stages: (1) Analyze the
circuit and cluster the standard cells according to the connectivity and the
slack, and then floorplan the clusters to minimize the number of standard
cells with negative slack and white space. (2) For fixing timing violation,
assign the supply voltage of the standard cells with negative slack to high
supply voltage. Under timing constraint, we reassign the supply voltage
of the standard cells with high supply voltage to reduce power
consumption. (3) Divide each mixed voltage cluster which contains high
supply voltage cells and low supply voltage cells into two single supply
voltage clusters. These clusters will contain only high supply voltage cells
or low supply voltage cells. After the voltage island formation, if the
timing constraint is not met, the voltage scaling refinement process will
be repeated. (4) Use the floorplan refinement process to minimize the
requirement of power-network resource and the white space. We use four
cases in the ISCAS89 benchmarks, and the experimental results show that
our algorithm is very effective in reducing the power consumption and
the requirement of power-network resource. On average, our algorithm
reduces the power consumption by 50.52% and reduce the requirement of
power-netrwork resource by 27.90%. Finally, the white space compared
to the total area of floorplan layout is about 3.58% on average.

並列關鍵字

voltage island ； power-network resource ； voltage scaling ； floorplan stage

參考文獻

[22] 蔡雅雯,”平面規劃階段之雙重電壓源元件置換及電壓島建構”, 中原大學資

2004, pp. 321-324.

[2] J. Pangjun and S. S. Sapatnekar, “Clock Distribution Using Multiple Voltages,”

Proceedings of International Symposium on Low Power Electronics and Design,

August, 1999, pp. 145-150.