平面規劃階段之雙重電壓源元件置換及電壓島建構

Dual Supply Voltage Scaling and Voltage Island Construction at Floorplan Stage

蔡雅雯(Ya-Wen Tsai)

指導教授 ： 陳美麗

中原大學/工學院/資訊工程研究所/碩士(2007年)

https://doi.org/10.6840/cycu200700552

摘要

在IC產業進入深次微米(Deep Submicron)的時代後，可攜式電子產品的功能需求越來越複雜，晶片上的功率消耗也隨之提升。因此，在現代的晶片設計中，如何降低晶片的功率消耗，成為一個相當重要的問題。雙重電壓源設計能有效率地降低晶片的功率消耗，並且不影響電路的時序。本論文使用雙重電壓源設計，提出ㄧ個在平面規劃階段配派標準元件工作電壓的演算法並規劃出電壓島區域，降低晶片功率消耗以及電壓網路資源(Power-Network Resource)的需求量。
本論文提出之演算法可分為四個步驟：(一)將連線關係緊密且slack值同為正或是同為負的標準元件規劃為同ㄧ群組，並以電路違反時序限制的標準元件數目及電路佈局中未使用到的面積(White Space)做為考量，來對標準元件群組做平面規劃；(二)將slack為負之標準元件配派為高電壓以修正時序錯誤，並在符合電路時序限制之下，對所有高電壓標準元件依照其power gain配派其工作電壓，改善功率消耗；(三)將ㄧ包含低工作電壓標準元件以及高工作電壓標準元件的標準元件群組，在符合時序限制之下，分割成ㄧ高工作電壓群組及一低工作電壓群組，使得每個標準元件群組均只包含單一工作電壓(高工作電壓或是低工作電壓)；(四)以電壓網路資源(Power-Network Resource)的需求量以及電路佈局中未使用到的面積(White Space)為考量，來改善平面規劃。從實驗結果可以看出，在ISCAS的四個測試電路上，我們的演算法能有效的減少電路的功率消耗及電壓源網路資源的需求，平均能夠達到47.3%的功率消耗改善。平均電路佈局中未使用到的面積(White Space)為電路佈局總面積的4.09%。
關鍵字：雙重電壓源設計、平面規劃階段、電壓島區域、電壓網路資源(Power-Network Resource)。

關鍵字

電壓網路資源 ； 雙重電壓源設計 ； 電壓島區域 ； 平面規劃階段

並列摘要

In the period of Deep Submicron Technology, the functions of portable electronic products are getting more and more complex, and the power consumption of the chips is also highly increased. Therefore, it’s a very important issue to reduce the power consumption of the chips in the modern VLSI designs. Using dual supply voltages on VLSI designs is an efficient method to reduce power consumption and maintain the circuit performance. In this paper, we proposed a voltage scaling, voltage island generation algorithm in the floorplanning stage to reduce power consumption and the requirement of power-network resource by using dual supply voltage.

Our algorithm includes the following four stages: (1) Cluster the standard cells according to the connectivity and the slack. Floorplan the clusters to minimize the number of standard cells with negative slack and white space. (2) Assign the supply voltage of the standard cells with negative slack to high supply voltage. Use voltage scaling refinement under timing constraint to reduce power consumption. We reassign the supply voltage of the standard cells with high supply voltage according to their power gain. (3) Divide each mixed cluster which contains high supply voltage cells and low supply voltage cells into two single supply voltage clusters which contain only high supply voltage cells or low supply voltage cells under the timing constraint. (4) Use the floorplan refinement to minimize the requirement of power-network resource and the white space. We tested four ISCAS benchmarks, and the experimental results show that our algorithm is very effective in reducing the power consumption and the requirement of power-network resource. On average, our algorithm reduces the power consumption by 47.3%. And the average white space compared to the total area of floorplan layout is about 4.09%.

並列關鍵字

voltage scaling ； floorplan stage ； voltage island ； power network resource

參考文獻

[1] J. N. Kozhaya and L. A. Bakir, “An Electrically Robust Method for Placing Power Gating Switches in Voltage Islands,” Customer Integrated Circuits Conference, 2004, pp. 321-324.

[5] K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanazawa, M. Ichida and K. Nogami, “Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor,” IEEE Journal of Solid-State Circuits, 1998, pp. 463-472.

[6] S. N Kulkarni, A. N. Srivastava and D. Sylvester, “A New Algorithm for Improved VDD Assignment in Low Power Dual VDD Systems,” Proceedings of International Symposium on Low Power Design, Aug., 2004, pp. 200-205.

[7] Y. Yeh and S. Kuo, “An optimization-based low-power voltage scaling technique using multiple supply voltages,” IEEE International Symposium on Circuits and Systems, Volume 5, 6-9 May 2001, pp. 535-538

[8] W. Hung, Y. Xie, N. Vijaykrishnan, M. Kademir, M. J. Irwin and Y. Tsai, “Total Power Optimization through Simultaneously Multipla-VDD Multiple-VTH Assignment and Device Sizing with Stack Forcing,” Proceedings of the International Symposium on Low Power Electronics and Design, 2004, pp. 144-149.