使用定向自組裝於一維格狀佈局之切點分佈與導引樣板分配

Cut Redistribution and Guiding Template Assignment Using DSA for 1D Gridded Layout

徐沛諠(Pei-Hsuan Hsu)

指導教授 ： 湯松年 ； 林佑政

中原大學/電機資訊學院/資訊工程研究所/碩士(2017年)

https://doi.org/10.6840/cycu201700554

摘要

摘要
許多半導體業者漸漸傾向於把複雜的二維設計(2D design)轉成高規則性的一維格狀設計(1D gridded design)，在這轉換過程中，切點(Cut)的分佈位置就成了最主要的挑戰，對於較先進的奈米設計，切點可能會太過密集，導致無法使用193nm immersion (193i)光刻技術切割，因此有些研究者提出一些其他的辦法，例如：Self-Aligned Double Patterning (SADP)、高解析度的E-Beam Lithography(EBL)和定向自組裝(Directed Self-Assembly，DSA)，而DSA在近幾年的研究中，表現出色，是一個有很大潛能的選項。在一維格狀設計中，佈局線段(Layout wire)是透過Metal cuts將Dense parallel lines劃分為Real wire和Dummy wire，Real wire是實現目標電路的功能，剩餘線段則稱為Dummy wire，為了維持原始佈局功能，切點的位置只能在Dummy wire中移動。
在佈局中，兩切點之間如果同時符合以下三個條件：(1)所在之線段為Real wire，(2)距離小於設計規則(Design rule)，(3)切點不隸屬於同一個DSA樣板(DSA Template)，我們就稱之為Conflict；Conflict在Templates之間的條件亦是類似。在本篇論文中，我們將討論如何挑選適當的DSA Patterns來實現切點，產生跟原始電路功能相同的一維佈局，利用DSA Pattern會隨著導引樣板(Guiding Templates)不同而產生不同形狀或大小Patterns的特性，在我們的實驗中，將利用模擬退火演算法(Simulated Annealing)來進行Pattern的挑選，達到Conflict數量最小化的最佳化目標，之後透過後處理進行Double cut數量最大化。在Conflict數量方面，相較於Xiao等人的研究[14] ，我們可達到104150%的改進率，與Li的研究[7] 相比，也有56%的改進率。在Double cut部分，平均可達12.18592593%的切點數量增加率。

關鍵字

定向自組裝 ； 切點 ； 導引樣板 ； 模擬退火 ； 一維格狀佈局

並列摘要

Abstract
Many semiconductor industries gradually tend to transit from the complex 2D design to a high regularity of 1D gridded design. In this transition process, cut distribution position has become the most important challenge. For more advanced nanometer designs, cuts may be too dense to be printed by 193 nm immersion (193i) lithography. Many techniques have been proposed by excellent researchers, e.g.: Self-Aligned Double Patterning (SADP), high resolution E-beam lithography (EBL) and Directed Self-Assembly (DSA). DSA is a great potential option and outstanding in recent years. In 1D gridded design, the layout wire divides the dense parallel lines into real wires and dummy wires through metal cuts. Real wire is to achieve the function of the target circuit and the remaining line is called Dummy wire. In order to maintain the original layout function, the cut location can only be moved within the dummy wire.
In the layout, if the distance of two cuts on the same real wire is less than the design rule and cuts do not belong to the same DSA template, it’s called “Conflict”. The conditions of conflict between two templates are similar. In this thesis, we will discuss how to pick the appropriate DSA patterns to make cuts and produce 1D gridded design as the original circuit with the same function.
With the assignment of different guiding template, DSA pattern shape or size will follow the assignment. In our experiments, Simulated Annealing algorithm is applied to pick patterns for the conflict number minimization. In the post-processing phase after SA-Based matching, the number of double cuts is maximized. In terms of the number of Conflict, we can achieve an improvement rate of 104150% compared to the result of Xiao et al.[14] , and 56% improvement compared to Li's study[7] . In the Double cut stage, an average increase rate of 12.18592593% of the cut number.

並列關鍵字

DSA ； cut ； guiding template ； simulated annealing ； 1D gridded layout

參考文獻

[1] X. Bao, H. Yi. C. Bencher, L.W. Chang, H. Dai, Y. Chen, P.T. J. Chen, and H.S. P. Wong., “SRAM, NAND, DRAM Contact Hole Patterning using Block Copolymer Directed Self-assembly Guided by Small Topographical Templates”, Electron Devices Meeting (IEDM), IEEE International, 7.7. 1-7.7. 4, 2011

[2] S.Y. Fang, Y.X. Hong, and Y.Z. Lu, “Simultaneous Guiding Template Optimization and Redundant via Insertion for Directed Self-Assembly,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 1, pp. 156-169, 2017.

[3] S.Y. Fang, Y.X. Hong, and Y.Z. Lu, “Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-Assembly,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD '15). IEEE Press, Piscataway, NJ, USA, 410-417, 2015.

[5] S. Kirkpatrick, C.D. Gelatt Jr. and M. P. Vecchi: “Optimization by Simulated-Annealing”, Science, Vo1220, Number 4598,1983, pp671-680

[7] Y.C. Li, “Hybrid Lithography Optimization with DSA and E-Beam for 1D Gridded Layout”, Master thesis, National Tsing Hua University, Hsinchu, Taiwan, 2014.