記憶體時脈分支線路訊號完整性之分析與設計

Analysis and Design for DDR Clock Branch Traces

柯博文(Po-Wen Ko)

指導教授 ： 薛光華

中原大學/電機資訊學院/電子工程研究所/碩士(2020年)

https://doi.org/10.6840/cycu202000425

摘要

本論文主要是因為在實際線路上，DDR 時脈(Clock)在傳輸線分支再分支結
構上遭遇到訊號完整性(SI)的問題。
我們藉由以下的探討，來讓波形達到最佳狀態：
1. 對於訊號一開始從 IC 零件輸出到分支結構時，傳輸線阻抗如何與串接電阻 匹配，進而達到最佳阻抗匹配並減少訊號反射。
2. 傳輸線分支結構，藉由每條分支傳輸線的長度來了解訊號完整性的變化。
3. 利用接收端前的串阻及放置距離，如何來降低訊號反射。
最後，我們提出一個設計記憶體時脈分支傳輸線線路的準則，讓接收端波形
達到最佳的狀態。

關鍵字

記憶體時脈 ； 分支線路 ； 訊號完整性

並列摘要

This paper investigates that DDR Clock encountered the problem of signal
integrity (SI) on branch and branch structure of transmission lines.
We make the waveform to the best state through the following ways:
1. How to achieve the best impedance matching and reduce signal reflection
between impedance of transmission lines and series resistance when the signal is
initially output from IC to branch structure of transmission lines.
2. To understand the signal integrity (SI) in branch structure of transmission lines
through the different length of each branch transmission line.
3. Using the series resistance in front of the receiving port and replacement distance
to know how to reduce the signal reflection.
Through the above ways, we propose guideline in how to design the best
waveform in branch structure of DDR Clock transmission lines.

並列關鍵字

DDR Clock ； Branch Trace

參考文獻

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Mitigation of Longest Differential via Stubs on Transmission Waveform and Eye Diagram in a Thick Multilayered PCB,” IEEE Transactions on Components, Packaging and Manufacturing Technology， vol. 4, no. 10, Oct. 2014.