單一多晶矽閘極非揮發性記憶元件之研究

Study of Single Poly Gate Nonvolatile Memory Device

徐偉勝(Wei-Sheng Hsu)

指導教授 ： 鄭湘原

中原大學/工學院/電子工程研究所/碩士(2007年)

https://doi.org/10.6840/cycu200700163

摘要

隨著3C數位產品的不斷發展下，非揮發性記憶體近年來在半導體記憶元件的發展與研究上，其所扮演的角色是愈來愈重要。為了因應電子產品輕、薄、短、小、多功能的需求下，積體電路製程技術已由毫米、微米進入至奈米級的高積集密度，對於元件之性能標準也相對地更加嚴苛。EEPROM俱備快閃記憶元件中純電性抹除與寫入之優勢，但需要使用兩層以上的多晶矽閘極及光罩，如此使得製程成本提高不少。然而單一多晶矽閘極非揮發性記憶體可相容於邏輯製程，故可避免提高製程成本。

本論文主要研究在於分析利用兩個NMOS、兩個PMOS或N/P MOS各一個所組成之單多晶矽互補金氧半場效應記憶體(Single-poly pure CMOS memory，SIPPOS )之特性。首先以實際晶片進行量測分析，利用研究寫入及抹除速度之特性進一步找出寫入及抹除最佳的操作條件。最後以T-CAD製程模擬軟體和半導體電性模擬軟體對單多晶矽互補金氧半場效應記憶體標準元件進行相關電特性模擬研究，目的在於驗証1P1N2N2P 互補金氧半場效應記憶體寫入及抹除機制是否與預期相符合，並利用交互比較Id-Vd與Id-Vg電流特性之模擬值與量測值來進一步証明單多晶矽互補金氧半場效應記憶體之物理特性以及其可行性，藉以評估此非揮發記憶體之最佳化與微縮可能性。

關鍵字

非揮發性記憶體 ； 熱載子 ； 帶對帶穿遂

並列摘要

With continuous developing of 3C products, the nonvolatile memory plays a very important role and receives more and more research and development. In order to achieve the requirement of compactness, portability and multi-functions in electronic products, VLSI processing technologies has been scaled down from micron scale into nanometer scale for their high density integration. EEPROM has advantages of electrically erasing and programming capabilities, but usually requires at least two layers of poly-Si films and masks. The extra deposition layers and masks will increase the cost. Alternatively, the single poly processing can be well compatible with logic circuits processes, and thus avoid the high processing cost.

This study was focusing on analyzing electrical properties of single-poly pure CMOS (SIPPOS) non-volatile memory which was consisted of 1P MOS plus 1N MOS, two NMOS, and two PMOS. In the study, silicon chips were measured for electrical analysis. Firstly, writing and erasing speed are tuned for finding optimal conditions. Secondly, related electrical characteristics of standard single poly CMOS memory are simulated by process and device simulation TCAD tools. Thirdly, simulated and measured Id-Vd and Id-Vg results are compared and calibrated improving physical properties and reliability of single poly CMOS memory. Finally, these results can be used for evaluating those nonvolatile memories for their possibility in scaling down.

並列關鍵字

hot carrier ； nonvolatile memory ； BTBT

參考文獻

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