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金屬閘極與多晶矽閘極在高介電常數閘極介電層N型金氧半場效電晶體之研究

Study on Metal Gate and Poly-Si Gate NMOSFET with High-k Dielectric Gate

摘要


隨著製程技術的改進下,元件尺寸跟著愈縮愈小,為了改善閘極穿遂漏電流的增加,使用高介電常數的材料以取代二氧化矽來降低閘極穿遂漏電流的方式正廣泛的研究。本文藉由探討使用高介電常數閘極之n型電晶體在相同的高介電常數材料介電層、不同的閘極材料下,比較之間的基本電性之差異。實驗發現堆疊金屬閘極元件因製程的關係而沒有較好之表現。

並列摘要


Up to now, the device dielectric thickness scaling down to 1.1 nm, and device EOT will down to 0.65 nm in 2010 year by ITRS roadmap; thus a high-k material was used to replace silicon dioxide for direct-tunneling effect suppressing. In this thesis, we investigated electrical characteristic and leakage current induced device's degradation on different gate structures for nMOSFET integrated with high-k dielectric material. We identify MOSFET with poly-Si gate possess less gate leakage current and gate capacitance than device with metal gate. Using metal gate as a barrier later between Poly-Si and high-k dielectric layer, better nMOSFET characteristic can be found.

並列關鍵字

Metal gate High-K dielectric

參考文獻


Shiraishi, K.,Yamada, K.,Torii, K.,Akasaka, Y.,Nakajima, K.,Kohno, M.(2004).Physics in fermi level pinning at the poly Si/Hf-based High-K Oxide interface.IEEE Symposium on VLSI Technology Digest of Technical Papers.(IEEE Symposium on VLSI Technology Digest of Technical Papers).
Hayashi, T.,Nishida, Y.,Sakashita, S.,Mizutani, M.,Yamanari, S.,Higashi, M.(2006).Cost worthy and high perfrmance LSTP CMOS; Poly-Si/HfSiON nMOS and Poly-Si/TiN/HfSiON pMOS.(IEEE International Electron Devices Meeting).
葉文冠、簡昭欣、徐韶華(2008)。90奈米技術之高介電常數閘極電晶體在負偏壓溫度不穩定性之可靠度研究(碩士論文)。國立高雄大學電機工程學系。
Sze, S. M.(2002).Semiconductor devices physics and technology.New York:Wiley.

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