Up to now, the device dielectric thickness scaling down to 1.1 nm, and device EOT will down to 0.65 nm in 2010 year by ITRS roadmap; thus a high-k material was used to replace silicon dioxide for direct-tunneling effect suppressing. In this thesis, we investigated electrical characteristic and leakage current induced device's degradation on different gate structures for nMOSFET integrated with high-k dielectric material. We identify MOSFET with poly-Si gate possess less gate leakage current and gate capacitance than device with metal gate. Using metal gate as a barrier later between Poly-Si and high-k dielectric layer, better nMOSFET characteristic can be found.