盲源分離訊號處理應用於多離子感測系統之晶片化實現

Blind Source Separation Processing on Multi-ion Sensing System with Chip Integration

李家緯(Chia-Wei Lee)

指導教授 ： 鍾文耀

中原大學/工學院/電子工程研究所/碩士(2011年)

https://doi.org/10.6840/cycu201100746

摘要

水質監控是現代生活重要的議題，為了有效地辨別水中所含離子的種類，及如何有效地得知與辨別原始訊號之變化，因此應用到盲源分離技術的理論，將水中離子有效地辨別。
本文研究重點主要為實現於多離子感測盲源分離系統，以離子濃度變化作為實驗設計考量，並且以此實驗設計考量作為盲源分離技術改變之特徵；首先將前端ISFET搭配橋式讀出電路，得到之訊號有效地經過盲源分離系統辨別其原始訊號，得到其主要離子及干擾離子變化之特徵曲線。本系統主要先根據整體系統讀出電路讀出電壓值關係，使用浮點數演算法來設計，進行硬體系統建置，將各式運算方法有效地實現在硬體上，並且使用各種Xilinx所提供之IP (Intellectual Property)來有效地縮短開發之時程，最後再利用FPGA進行整體系統之驗證，確認已達到功能後，則參考硬體架構開始進行verilog程式碼的撰寫，並且利用合成軟體Design Vision進行RTL合成，再使用自動佈局軟體IC Compiler進行晶片的佈局，最後進行CIC晶片下線與量測。

關鍵字

Verilog ； 浮點數 ； RTL ； 自動佈局 ； 盲源分離 ； 橋式讀出電路 ； ISFET ； FPGA

並列摘要

Water quality monitoring has become an important issue of modern life. For safe human consumption, it is necessary to determine the ion contents of water. Blind Source Separation (BSS) theory provides an effective means of ion identification.
This research focuses on the multi-ion sensing to achieve blind source separation system. In multi-ion chemical environment, the source signals correspond to the concentration of main ions and the concentration of interference ions. Experiments are conducted where the concentration of main ions is changed to predefined amounts as the concentration of interference ions is maintained constant. The mixtures of these source signals are measured using the Bridge-Type Readout Circuit of ISFET. Compared with known sample source signals, the BSS algorithm is confirmed to successfully estimate the original sources from the observed signals of ISFET readout circuit. The hardware systems that execute BSS function are designed based on the floating-point algorithm, complete any computing methods in hardware effectively, and are applied using the Xilinx Intellectual Property (IP) modules. Finally, the entire BSS design is embedded into a Field Programmable Gate Array (FPGA). Make sure function has been reached, and begin writing verilog code follow hardware architecture, and use synthetic software Design Vision to do RTL synthesis, and use automatic placement and routing software IC Compiler to do the chip layout. Finally follow the step to tape out CIC chip and measurement.

並列關鍵字

Verilog ； automatic placement and routing ； RTL ； Floating Point ； Field Programmable Gate Array (FPGA) ； Bridge-Type Readout Circuit ； ISFET ； Blind Source Separation

參考文獻

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