盲源分離訊號處理應用於尿路結石復發預防之多參數檢測系統

Application of Blind Source Separation Algorithm Synthesized on FPGA to the Multi-Sensor Plattform for Urolithiasis Detection

周明瑩(Ming-Ying Zhou)

指導教授 ： 鍾文耀

中原大學/電機資訊學院/電子工程研究所/碩士(2015年)

https://doi.org/10.6840/CYCU.2015.00485

摘要

本文研究重點主要為實現於多參數感測盲源分離系統，以離子濃度變化作為實驗設計考量，並且以此實驗設計考量作為盲源分離技術改變之特徵；首先將前端ISFET、EGFET搭配電壓式讀出電路，得到之訊號有效地經過盲源分離系統辨別其原始訊號，得到其主要離子及干擾離子變化之特徵曲線。本系統主要先根據整體系統讀出電路讀出電壓值關係，使用定點數演算法來設計，進行硬體系統建置，將各式運算方法有效地實現在硬體上，最後再利用FPGA(Field-programmable gate array)進行整體系統之驗證，確認已達到功能後，利用合成軟體Design Vision進行RTL合成，再使用自動佈局軟體IC Compiler進行晶片的佈局。

關鍵字

盲源分離 ； 主成分分析 ； ISFET ； 電壓式讀出電路 ； FPGA ； Verilog ； RTL

並列摘要

This research focuses on the implementation of a Blind Source Separation (BSS) algorithm system on a multi-parameter sensing platform. In the multi-ion chemical environment, the source signals correspond to the concentration of main ions and the concentration of interference ions. Experiments were conducted where the concentration of the main ions is changed to predefined amounts as the concentration of the interference ions is held constant. Ion-Sensitive Field Effect Transistor (ISFET) - based Potentiometric Readout Circuit was used to get raw data from these concentrations. Compared with the known sample source signals, the BSS algorithm has successfully estimated the original sources from the observed signals from the readout circuit. Hardware systems that execute the BSS function use the fixed-point algorithm thereby showcasing an efficient computational method. Finally, the entire BSS design is embedded into a Field Programmable Gate Array (FPGA). Firstly, the functionality of the BSS algorithm has been verified using MatLab. Then, the algorithm was implemented onto a verilog code into a hardware architecture. RTL synthesis was undergone using the synthetic software Design Vision. Finally, the automatic placement and routing software IC Compiler was used to implement the code into an Application Specific IC (ASIC) which can readily sent for fabrication using TSMC 0.18um CMOS 1P6M Mixed Mode Process.

並列關鍵字

Blind Source Separation ； Principal Component Analyis ； ISFET ； Potiental Readout Circuit ； Field Programmable Gate Array (FPGA) ； Verilog ； RTL

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