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  • 學位論文

使用特徵分析方法改良無樣態先之兩階段晶圓圖瑕疵辨識

Improving None-First Two-Stage Method with Feature Analysis for Wafer Map Defect Classification

指導教授 : 梁新聰

摘要


著半導體產業的蓬勃發展,製程也逐漸變得複雜,這使晶圓的價格非常昂貴,良率也因此成為重要的指標。在晶圓製造的過程中可能因為機台的問題或是人為因素影響到晶圓的良率,而工程師可以透過機台產生出的晶圓圖來去追溯造成的問題的根本原因(Root Cause)來去故障檢修 (Trouble shooting ),所以晶圓圖分析也成了一個相當重要的議題。在以往通常是以人工目檢的方式篩選不符合條件的晶圓,並以工程師自身的經驗判斷造成晶圓圖上瑕疵樣態的根本原因,這過程耗費大量的人力與時間成本,所以我們建立一個自動化辨識晶圓的系統加速問題的排除使提升良率及降低成本。本論文可以分為兩個部分,第一部分先使用聚類演算法DBSCAN留下晶圓圖上的主要缺陷,再以特徵分析進行辨識,標記瑕疵樣態於晶圓圖的所在位置,運算時間為8.23ms/wafer。第二部分為基於第一部分的架構結合深度學習的方法,提升辨識精度,解決了監督式學習在晶圓圖上有多個瑕疵樣態時僅能得出一個結果的問題,總體平均辨識精度為94.1%。

並列摘要


With the prosperity of the semiconductor industry, manufacturing processes have become increasingly complex, making wafers be very expensive and yield be an important indicator. In the process of wafer fabrication, wafer yield may be affected by machine or human factors. Engineers can analyze wafer bin maps to trace root causes of occurred problems. In the past, wafers usually were screened by manual visual inspection and engineers' own experience. This paper can be divided into two parts. The first part uses the clustering algorithm DBSCAN to collect cluster defects on wafer maps and recognize them by our feature analysis method. We can mark the location of defect patterns on wafer maps, with 8.23ms of computation time for each wafer. The second part is based on the first part and combined with deep learning method to improve recognition accuracy, solving the problem that supervised learning can only recognize one result when there are multiple defect patterns on a wafer map. Our overall average recognition accuracy is 94.1%.

參考文獻


[1] 呂東穎, "Application of Wafer Map Partition Analysis to Enhance the Salient Pattern Identification", 碩士論文, 中央大學, 2019.
[2] Jung Yoon Hwang, and Way Kuo, "Model-Based Clustering for Integrated Circuit Yield Enhancement.", European Journal of Operational Research , Volume: 178, Issue: 1, pp. 143-153, 1 April 2007.
[3] Ming-Ju Wu, Jyh-Shing R. Jang, and Jui-Long Chen, "Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets", IEEE Transactions on Semiconductor Manufacturing, Volume: 28, Issue: 1, pp. 1 - 12, Feb 2015.
[4] 張嘉修, "NFTS: A None-First Two-Stage Model for Wafer Map Defect CLassification", 碩士論文, 中央大學, 2021.
[5] Mengying Fan, Qin Wang, and Ben van der Waal, "Wafer Defect Patterns Recognition Based on OPTICS and Multi-Label Classification," in Proc. IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC), pp.912-915, Oct. 2016.

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