晶片製程變異感知之頂層閘控制時鐘樹合成方法研究

On-Chip-Variation-Aware Top-Level Gated Clock Tree Synthesis

王得睿(Te-Jui Wang)

指導教授 ： 黃世旭

中原大學/電機資訊學院/電子工程研究所/碩士(2016年)

https://doi.org/10.6840/cycu201600078

摘要

隨著製程技來到了奈米等級，元件尺寸不斷的縮小，使得晶片製程變異的影響越來越深，使得時鐘樹合成越來越受到挑戰，原因在於製程變異會使得元件時序有誤差，便會使得時鐘樹時序錯誤，然而也隨著製程進步，也使得時鐘樹的功率消耗佔據了整體晶片的功率消耗的一半，而時鐘閘控制技術是目前非常有效於降低時鐘樹功率消耗的方法之一，為了考量功率消耗以及製程變異，本篇論文中，我們提出了兩個考慮晶片製程變異的頂層閘控制樹合成的方法，其中一個方法為啟發式演算法，主要利用成本函式進行模組間合併的挑選，增強模組間的鬆弛時間以及減少非共用路徑長度，接著再以艾爾蒙延遲模型進行時鐘閘控制樹繞線，以達到低時序差異，而另一個方法為混合整數線性規劃方法，我們將製程變異問題轉化為混合整數線性規劃方法，利用混合整數線性規劃方法找出在考慮製程變異下最佳的頂層閘閘控制樹拓樸，實驗結果顯示，啟發式演算法與混合整數線性規劃方法可以提升模組之間最壞鬆弛時間10.8%與8.3%。

關鍵字

晶片製程變異 ； 頂層閘時鐘樹 ； 時鐘閘 ； 最壞鬆弛時間

並列摘要

The objective of top-level clock tree synthesis is to construct the clock tree for connecting different sub-blocks. In advanced process technology, on-chip variation (OCV) effect has become more and increase the uncertainties on clock paths. Thus, there is a need to find good divergence points in the top-level clock tree to reduce the OCV effects on the non-common paths for minimizing the clock uncertainties, especially for those sub-blocks that have critical paths between them.
In advanced VLSI design, the power consumption of clock tree is around 50% in the entire chip. In practice, during circuit execution, there is only a portion of circuit is active. Therefore, clock gating technique, which shut down unused sub-blocks, is a useful technique to reduce the power consumption.
Based on this observation, in this thesis, we study the top-level gated tree synthesis approach. We propose a heuristic algorithm and a mixed integer linear programming approach to maximize the worst slack under non-common path length constraint and power consumption constraint. Benchmark data consistently show that our heuristic algorithm and mixed integer linear programming approach can achieve good results.

並列關鍵字

Top-Level Gate Tree ； OCV ； Worst Slack ； Non-common path

參考文獻

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