應用小波轉換與人工智慧進行具偵測與修正比流器飽和功能之過電流電驛晶片設計

Application of Wavelet Transform and Artificial Intelligence for Designing Overcurrent Relay Chip of Detecting and Correcting Saturated Current Transformer

張簡博全(Po-Chuan Chang-Chian)

指導教授 ： 洪穎怡

中原大學/工學院/電機工程研究所/碩士(2006年)

https://doi.org/10.6840/cycu200600428

摘要

過電流電驛依其反時特性曲線之設定，經常被使用在電力系統輸配線路及電力設備的保護，以防止線路及設備因異常狀況下之過載或短路造成損壞，目前電驛由傳統之電磁式及固態式演進至數位式之電腦(數位)電驛，其又可由微處理機、單晶片或更高級的數位信號處理晶片實現。而「場可規劃閘陣列」(FPGA)晶片之掘起，提供了比數位信號處理晶片更廉價且更具設計彈性之性能。
另一方面，過電流電驛一般由前端比流器取其二次側信號，傳入電驛進行有效值計算，然而當故障發生時，往往產生極大電流並帶有直流成份，造成比流器飽和，使得傳入電驛之電流發生畸變，而比實際值來得小，因此會使電流電驛誤動作，甚至沒有動作，而引起系統不穩定或設備之損壞，進而造成重大的經濟損失。因此本文發展一可自動偵測與修正電流信號畸變之泛用型過電流電驛晶片，此晶片可做為未來發展智慧型電子元件之雛型。
本文以小波轉換先偵測每一週波之瞬間二次電流值，以判斷每一週波畸變開始與結束時間，以便進行修正。另外再以多層感知機類神經網路進行畸變波形之修正，然而類神經網路所訓練之資料過於龐大，且發生畸變之情形太多，故必須將訓練資料分類，以個別訓練多個多層感知機神經網路來加速收斂時間。本文以模糊C分割法將資料分成九類。訓練完成後之九個類神經網路，於測試或線上使用時，則透過九個Takagi-Sugeno-Kang模糊規則合成最後結果。本文以晶片設計之Verilog硬體描述語言實現上述小波轉換、多層感知機類神經網路及Takagi-Sugeno-Kang模糊規則，並設計成矽智產模組，而模糊C分割及類神經訓練則在個人電腦執行。接著再增加IEC 255-3過電流反時特性曲線於晶片內，以達到泛用型過電流保護之目的。傳統設計上反時特性曲線必須消耗大量的邏輯閘元件。為了解決此問題，本文之泛用型過電流保護功能，分以下四個矽智產模組設計: (1)延時模組包含四組參數的一個類神經網路，以描述反時特性曲線，(2)計時模組在接收延時跳脫命令後開始計算時間，(3)決策模組依設定之電驛參數決定一組類神經網路權重值參數，(4)比較模組依計時模組與延時模組輸出，適時送出跳脫信號。
最後本文使用MATLAB/SIMULINK模擬一161 kV傳輸線保護系統、22.8 kV配電保護系統及電動機保護系統，並取其模擬之結果，來驗證晶片之精確度及其功能符合設計之要求。

關鍵字

模糊理論 ； 晶片設計 ； 數位電驛 ； 類神經網路 ； 小波轉換

並列摘要

The overcurrent relays depending on the inverse-time characteristics are used always in the power system for protecting transmission /distribution lines and power apparatuses from overcurrent. The evolution of protective relays started from electromagnetic/solid-state relays through single micro-processor to multiple digital signal processors (DSP). Due to development of Field Programmable Gate Array (FPGA), FPGA provides a cheaper chip and more flexible design compared with the DSP chip.
On the other hand, the overcurrent relay employs the secondary current from the current transformer (CT) for evaluating RMS values and then determines the operation action. However, a large current incorporating with DC offset will cause the CT to be saturated when the fault occurs. When the CT saturates, the secondary current becomes distorted and smaller than the actual value. This condition will result in relay malfunction and cause the system unstable or the facility damaged. It will also cause great pecuniary loss. Therefore this thesis develops a overcurrent relay chip of automatic detecting and correcting saturation of the current transformer. This chip can be developed further to be a prototype of intelligent electronic device (IED) in the future.
The wavelet transform were adopted to detect the distortion portion of the CT instantaneous secondary current in each cycle. The starting and ending instants of a distortion period were identified for compensating. The multi-layer feed-forward neural network were used to correct distorted waveform. The fuzzy-c-means were used to classify the training data into nine clusters because of a large number of data and diversified scenarios. Hence, the convergence speed of the neural network can be improved due to individual training data. The well-trained nine neural networks were used for testing and on-line application. The Takagi-Sugeno-Kang fuzzy rules were considered to attain the final inference from the nine neural network outputs. The above wavelet transform, multi-layer feed-forward neural network and Takagi-Sugeno-Kang fuzzy rules were designed by Verilog Hardware Description Language (VHDL) in a Silicon Intellectual Property (SIP) module. The fuzzy-c-means algorithm and neural network training were conducted in a PC. The developed chip were enhanced to include the IEC 255-3 overcurrent inverse-time characteristics for achieving the purpose of universal use. Traditional IEC 255-3 overcurrent inverse-time characteristics design consume great number of logic element. To cope this problem, the following four SIP modules were developed for achieving function of universal overcurrent protection: (1) Inverse-time module employ the neural networks for computing the inverse (delayed) time of overcurrent relays. (2) Timer module compute time after receiving the delayed tripping command from the determination module. (3) Determination module employ relay setting value to determines one out of the 4 sets of known weightings for the neural networks depending on 4 types of overcurrent relays. (4) Comparison module receives signals from the inverse-time/timer modules and makes a decision for tripping.
This thesis simulates a 161 kV transmission line protection system, 22.8 kV distribution line protection system and motor protection system by Matlab/Simulink. The overcurrent values were be attained from simulation results to validate the precision of the FPGA chip design and verify the function of the designed chip.

並列關鍵字

Wavelet Transform ； Neural Network ； Fuzzy Set Theory ； Digital Relay ； Chip Design

參考文獻

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