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  • 學位論文

應用限制驅導式於晶圓廠等候時間限制之產能規劃

Application of Drum-Buffer-Rope to the Capacity Planning of Wafer Fabrication with Time Constraint

指導教授 : 陳建良
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摘要


晶圓製造過程為避免晶圓受污染而影響良率以及產出,會在清洗及烘烤後加上等候時間限制。晶圓若未在時間限制內至下一個工作站加工,則須送回上一步驟或某些特定步驟重新加工。因此在製品存量過多之情形若發生在晶圓廠等候時間限制製程中,將使晶圓暴露在空氣中的時間增加,造成晶圓受塵埃微粒污染,導致大量等候中的在製品重加工。限制理論指出瓶頸資源的產出是整體系統產出之關鍵,因此若能在等候時間限制製程中考慮瓶頸機台前在製品存量之多寡,將可避免大量在製品數超過等候時間限制設定值造成晶圓重加工之情況,充分利用系統資源,減少產能耗費以及成本支出。 本研究針對晶圓製造後段製程發展等候時間限制下之產能規劃系統,以解決晶圓廠因等候時間限制而造成在製品堆積導致重工以及產能耗費之問題,藉由限制驅導模式之緩衝區大小設定決定時間限制內期望在製品存量,並藉由投料機制牽引時間限制製程之上游機台維持系統內在製品水準,達到同步生產。在限制驅導模式之績效驗證上利用模擬模式建立並搭配反應曲面分析,尋找緩衝區大小設定與等候時間限制設定值之最佳組合。實驗結果顯示限制驅導模式於不同生產環境下,均能有效降低晶圓重工率以及減少產能損耗,並充分利用系統資源,提供管理者快速訂立等候時間限制相關決策之依據。

並列摘要


Time constraint is applied after the cleaning and banking process to avoid wafer contamination in semiconductor manufacturing. Any lot failing to meet the time constraint needs to be reworked. Therefore, it is important to control the work-in-process (WIP) level to reduce the number of lots whose waiting time exceeds the time constraint. From the viewpoint of Theory of Constraints (TOC), bottleneck machine governs the system throughput. Therefore, it is critical to control the WIP level in front of the bottleneck machine in the process with time constraint requirement. This research develops a capacity planning system (CPS) for the backend process of semiconductor manufacturing with reentrant process. CPS applies TOC to manage time constraint, so lot rework and capacity loss can be minimized. CPS determines the expected WIP level using TOC’s Drum-Buffer-Rope mechanism and then controls wafer release to meet the expected WIP level. The best combination of WIP level and time constraint is identified by simulation study and response surface analysis. Simulation results reveal that CPS can significantly reduce lot rework and capacity loss in different production scenarios.

參考文獻


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