用於晶圓瑕疵辨識的幾何特徵統計分析

Statistic Analysis of Geometric Features for Wafer Defect Recognition

林彥成(YEN-CHENG LIN)

指導教授 ： 梁新聰

中原大學/電機資訊學院/電子工程學系/碩士(2022年)

https://doi.org/10.6840/cycu202201278

摘要

近年來半導體工業技術與時俱進，晶圓製造流程技術的提升，晶圓產出的良率也勢必有所進步，透過晶圓測試找出晶圓瑕疵，進而找出工藝流程上的問題，並讓工程師作出判斷以及調整錯誤，減少製造成本。本文提出晶圓瑕疵圖的幾何特徵參數提取，首先對公開資料集WM-811K使用多項預處理工作，接著運用簡單的演算法，成功提取晶圓瑕疵樣態的幾何特徵參數，製作出特徵參數區間表，將待測試的晶圓瑕疵圖做落點分析，以分析晶圓瑕疵圖的幾何意義及其特性。實驗分析表示， Near-Full的特徵參數分布集中是較明顯的晶圓瑕疵樣態，這些參數數值有助於提升特徵參數區間表的準確度，在判斷落點分析有顯著的效益。

關鍵字

晶圓圖 ； 瑕疵樣態辨識 ； 特徵參數分析

並列摘要

In recent years, the technology of the semiconductor industry has advanced with the times. Wafer fabrication process technology enhancement, and the yield of wafer production is bound to improve. Wafer testing is used to identify wafer defects, which leads to process problems and allows engineers to make judgments and adjust errors to reduce manufacturing costs. In this paper, we propose geometric feature extraction for wafer defect maps, first using several pre-processing efforts on the public data set WM-811K. Then, a simple algorithm was used to extract the geometric parameters of the wafer defect samples, and a table of feature parameters was created. The wafer defect map to be tested is analyzed for its geometric meaning and characteristics. The experimental analysis shows that the distribution of the geometric feature parameters of Near-Full is focused on the more obvious wafer defect patterns. These parameter values help to improve the accuracy of the feature parameter interval table, which has significant benefits in determining the landing analysis.

並列關鍵字

Wafer bin map ； Defect pattern recognition ； Feature parameter analysis

參考文獻

[1] 呂東穎, "Application of Wafer Map Partition Analysis to Enhance the Salient Pattern Identification", 碩士論文, 中央大學, 2019.

[2] Ming-Ju Wu, Jyh-Shing R. Jang, and Jui-Long Chen, Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets, IEEE Transactions on Semiconductor Manufacturing, Volume: 28, Issue: 1, pp. 1 - 12, Feb 2015.

[3] 張嘉修, "NFTS: A None-First Two-Stage Model for Wafer Map Defect CLassification", 碩士論文, 中央大學, 2021.

[4] 黃柏霖, “Improving None-First Two-Stage Method with Feature Analysis for Wafer Map Defect Classification,” 碩士論文, 中原大學, 2022.

[5] M. Saqlain, B. Jargalsaikhan and J. Y. Lee, “"A Voting Ensemble Classifier for Wafer Map Defect Patterns Identification in Semiconductor Manufacturing",” IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 32, NO. 2, May 2019.