並列摘要
In the clock network design, the trade-off between power consumption and timing closure has been one of the main goals in integrated circuits design. Hybrid clock network architecture combines the advantages of both clock tree and clock mesh to achieve a balance between power consumption and timing closure. In addition, clock gating technique can effectively reduce dynamic power consumption, but the timing closure is also important. In this thesis, we propose a novel clock mesh architecture - Cross Mesh, with the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees, and also reducing the use of clock gate resources. Experimental results show that our approach can get feasible solution and effectively improve power consumption and clock skew.