電源閘控制電路之激增電流最小化

現今的製程技術持續邁向更先進甚至到奈米階段，所以如何降低漏電流成為一大關鍵。許多提出的理論中，電源閘控制是最有效率降低漏電流的技術。因此我們利用電源控制電路在閒置功能單元中有效地降低漏電流。然而，當此功能單元被打開時，會產生一股大電流流出，稱之為激增電流。假如很多的功能單元同時地被打開，這時候瞬間會產生較大的激增電流可能導致電路的功能錯誤。為了解決激增電流所帶給電路的功能錯誤問題，在此篇論文中，我們指出在高階合成下(包含運算排序和功能單元繫結)對於最大的激增電流有很大的影響。另外我們發現在相同的漏電流限制下，不同的高階合成結果也會導致不同的最大激增電流值。然後，根據觀察，我們在高階合成階段下提出以混合型整數線性規劃的方式來正式定義激增電流最小化的問題和在相同的漏電流限制下定義激增電流最小化的問題。與現行的設計流程相比較下，由實驗結果顯示我們的方法可以在沒有違反任何額外合成限制條件下有效地降低最大的激增電流。

關鍵字

功能單元繫結；運算排序；整數線性規劃；電源閘控制；激增電流

並列摘要

Nowdays, the process technology is scaling from deep sub-micron tonano-meter regime, it is important to reduce leakage power. Among various methods, the power gating is the most effective technique to reduce the leakage power. Thus, we use the power gated circuits to reduce the leakage power of an idle function unit. However, when the functional unit is turned on, a sudden discharge called surge current, is induced. If too many functional units are turned on simultaneously, the instantaneous accumulated surge current may lead to the malfunction of the circuit. In order to solve this problem, in this thesis, we point out the high-level synthesis (include operation scheduling and functional unit binding) has a great impact on the maximum surge current. In addition, under the same leakage power constraint, we discover that the different high-level synthesis results lead to different maximum surge currents. Then, based on that observation, we propose two mixed-integer linear programs (MILP): one MILP to formally draw up the surge current minimization problem, and the other one MILP to formally draw up the leakage-power-driven surge current minimization problem. Compared with the existing design flow, benchmark data show that our approach can significantly reduce the maximum surge current without any design overhead.

並列關鍵字

Functional Unit Binding ； Operation Scheduling ； Integer Linear Programming ； Surge Current ； Power Gating

參考文獻

[1] Semiconductor Industry Association, “International Technology Roadmap for Semiconductors”, 2001.

[2] R.K. Krishnarnurthy, A. Alvandpour, V. De, and S. Borkar, “High-Performance and Low-Power Challenges for Sub-70 nm Microprocessor Circuits”, Proc. of IEEE Custom Integrated Circuits Conference, pp. 125—128, 2002.

[3] J. Kao, S. Narendra, and A. Chandrakasan, “MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns”, Proc. of IEEE/ACM Design Automation Conference, pp. 495—500, 1998.

[4] C. Long and L. He, “Distributed Sleep Transistor Network for Power Reduction”, Proc. of IEEE/ACM Design Automation Conference, pp. 181—186, 2003.

[7] H.-O. Kim and Y. Shin,”Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications”, IEEE Trans. on Circuits and Systems II, vol. 54, no. 6, pp. 512—516, 2007.

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電源閘控制電路之激增電流最小化

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