峰值電流最小化之狀態編碼公式化

中文摘要隨著積體電路製程技術進步，其設計複雜度增加及工作頻率提高，暫存器的個數也隨之增加，瞬間造成瞬間峰值電流(Peak Current)越來越大，而瞬間峰值電流變大後會在積體電路(Integrated Circuit)元件內產生壓降效應(Voltage Drop)，進而造成電路內部動作錯誤，本篇目標主要為利用狀態編碼的方式來降低峰值電流，對各狀態編碼去分析峰值電流提出ILP公式與定義，本篇利用ILP計算軟體來進行實驗分析，先前文獻[2]，雖已提出一些狀態編碼方法，但其主要著重在平均消耗功率上，參考先前文獻 [3][4][5]，平均消耗功率與電路傳輸路徑各狀態所有切換次數(switching activities)成正比，另外文獻[6]所提的雖也是降低峰值電流的方式，但它所利用的是狀態重新編碼(Re-encoding)，其方法是就現有狀態碼予以重新編碼(Re-encoding)，只是暫存器上切換方向可能有所調整，本篇文獻與文獻[6]觀念並不相同，本篇論文主要是採用整數線性規劃(Integer Linear Program, ILP)來定義出公式，找出最小峰值電流之狀態編碼。

關鍵字

狀態編碼；有限狀態機；整數線性規劃；峰值電流

並列摘要

Abstract The design complexity and operation frequency of integrated circuits are getting higher as the semiconductor technology progresses in last decades. Meanwhile, the number of register accommodated in a circuit increases as well. Unfortunately, it results in a large peak current consumption in a short instant, consequently an undesired voltage drop occurs, which may lead to malfunction of the system. This thesis aims at reducing the peak current by means of state encoding of a circuit. An ILP formulation is proposed to reduce the peak current characteristics based on various state coding schemes. Referring to the prior research, such as [1] [2], it shows that they are all focused on the exploration of average power consumption. Whereas, [3][4][5] are mainly discussing the proportionality of average power consumption with respect to the switching activities of signal path states. On the other hand, [6] presented a method of re-encoding the original state codes for peak current reduction, which is substantially different with our scheme. In this thesis, we use an Integer Linear Program (ILP) methodology to find out the best state codes for minimum peak current.

並列關鍵字

Peak Current ； Finite State Machine ； State Encoding ； Integer Linear Programming

參考文獻

[1] L. Benini and G.D. Micheli, “State Assignment for Low Power Dissipation,” IEEE Journal of Solid State Circuits, vol. 30, no. 3, pp. 258—268, 1995.

[2] W. Noth and R. Kolla, “Spanning Tree Based State Encoding for Low Power,” Proc. of IEEE/ACM Design, Automation, and Test in Eurpoe, pp. 168—174, 1999.

[3] C.Y. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. Despain, and B. Lin. “Power Estimation Methods for Sequential Logic Circuits,” IEEE Trans. on VLSI Systems, vol. 3, no. 3, pp. 404—416, 1995.

[4] K. Roy and S. Prasad, “Circuit Activity Based Logic Synthesis for Low Power Reliable Operations,” IEEE Trans. VLSI Systems, vol. 1, no. 4, pp. 503—513, 1993.

[5] J.M. Rabaey and M. Pedram, “Low Power Deisgn Methodologies,” Kluwer Academic Publishers, 1996.

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峰值電流最小化之狀態編碼公式化

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