考慮測試功率、可壓縮性、以及電壓降效應之測試向量產生方法

Scan Test Pattern Generation Considering Test Power, Compressibility, and IR-Drop Effects

吳孟帆(Meng-Fan Wu)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2010年)

https://doi.org/10.6342/NTU.2010.01645

摘要

掃描鏈測試是積體電路測試中廣泛使用的方式，而自動測試向量產生方法已經被研究了數十年。雖然自動測試向量產生方法是傳統的設計自動化問題，現代低電壓、高頻、高複雜度的設計已經大幅改變了此問題。因此，在產生向量檔的過程中，還需要同時去考慮各種不同的問題。例如，測試功率的消耗、測試向量的壓縮、以及全速測試過程中過量的電壓降對良率的影響。假如我們能在測試向量產生過程中考慮這些問題，將能夠提升測試向量檔的品質。

在這份論文當中，我們提出了數個演算法在產生測試向量檔的同時，考慮測試功率、可壓縮性、與電壓降效應。這份論文在一開始提出了一個新技術，來減少基本的測試過程中測試功率以及引發之電壓降。之後，我們提出新的技術將典型的電壓降減少方法成功地應用到測試向量壓縮環境。最後，為了減少因電壓降估算誤差所造成的可靠度下降，我們提出了一個快速的，藉由考慮電源網架構來增加精確度的電壓降估算方法。

關鍵字

積體電路測試 ； 低功率測試 ； 電壓降關切測試 ； 測試向量壓縮

並列摘要

Scan testing is a widely used test methodology in the industry and the automatic test pattern generation (ATPG) problem has been studied for several decades.Although ATPG is a classical problem, modern high operating frequency, low-power, and high complexity circuit designs have posed new challenges. Thus, during test pattern generation, in addition to fault coverage and test pattern count, one has to consider test power dissipation, test pattern compression, and excessive IR-drop effects on at-speed scan testing. If we can consider above issues while generating test patterns, the test set quality could be improved.
In this dissertation, we propose several algorithms and techniques to consider test power dissipation, test compressibility, and IR-drop effects in ATPG. This dissertation starts with a new technique, which aims at reducing test power and IR-drop effects during the whole scan test application process. Next, we propose an efficient and effective flow to alleviate launch cycle IR-drop effects by minimizing launch cycle switching activity in the test compression environment. Finally, to improve the IR-drop estimation accuracy, we propose a scalable quantitative measure of IR-drop effects which improve the accuracy by considering the power grid structure.

並列關鍵字

VLSI Testing ； Low-Power Test ； IR-Drop-Aware Test ； Test Compression

參考文獻

Pattern Generation Considering Supply Voltage Noise in a SOC Design. In

Proc. Design Automation Conference, pages 533–538, 2007.

Power Scan Design Using First-Level Supply Gating. IEEE Transactions on

Very Large Scale Integration Systems, 13(3):384–395, Mar. 2005.

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded