以最小面積負擔達到時鐘週期下限之合成方法研究

Synthesis for the Lower Bound of Clock Period with Minimum Area Overhead

凃雯斌(Wen-Pin Tu)

指導教授 ： 黃世旭

中原大學/工學院/電子工程研究所/博士(2014年)

https://doi.org/10.6840/cycu201400543

摘要

為了提升晶片效能，時鐘週期最小化一直都是積體電路設計重要的研究議題。時序差異排序是一個有效降低時鐘週期之循序時序最佳化技術，過去已有許多研究探討利用時序差異排序來降低時鐘週期，其中有些方法甚至已可達到循序時序最佳化的下限。然而，這些方法在應用上卻仍有所限制。因此，在本篇論文中，我們分別在高階合成階段及邏輯合成階段，針對過去文獻之限制，提出更有效可以達到時鐘週期下限之設計方法。
在高階合成階段，過去的文獻只考慮時鐘訊號抵達暫存器時間對暫存器共享的影響，沒有考慮到時鐘訊號抵達暫存器時間對功能單元共享的影響，因此造成在功能單元繫結時會有額外的功能單元增加。基於以上觀察，我們在非零時序電路之高階合成，同時考慮時鐘訊號抵達暫存器時間對暫存器共享及功能單元共享的影響。我們的目標是電路運作在循序時序最佳化的下限前提下，來最小化增加面積的負擔。我們提出整數線性規劃的方法解決此問題，與過去的文獻比較，實驗結果表明了我們的方法可以有更小的面積負擔來運作在時鐘週期下限。
在邏輯合成階段，過去的文獻只考慮資料路徑之時序差異排序，然而一個時鐘閘控制設計包含了資料路徑與時鐘控制路徑兩者，所以過去文獻的考慮是不完整的。基於以上觀察，我們針對時鐘閘控制設計提出了資料路徑與時鐘控制路徑共同合成的方法，我們的目標是透過非零時序差異達運作在時鐘週期下限(同時考慮資料路徑與時鐘控制路徑之時鐘週期下限)，最小化所需要插入緩衝器造成的負擔。與過去文獻不同的是，我們的方法可以保證沒有違反任何時鐘閘控制的時序條件，實驗結果也顯示我們可以有效的提升電路速度且只造成極小的功率消耗負擔。

關鍵字

邏輯合成 ； 高階合成 ； 時鐘週期最小化 ； 最小化面積負擔 ； 時序差異排序

並列摘要

To improve circuit performance, clock period minimization is always an important topic in the design of integrated circuits. Clock skew scheduling is a useful technique for sequential timing optimization. Therefore, many research efforts were devoted to clock skew scheduling. Especially, some approaches can achieve the lower bound of the clock period. However, these approaches still have some limitations in applications. Therefore, in this dissertation, we propose two approaches, in the high-level synthesis stage and in the logic synthesis stage, respectively, to overcome the limitations of previous works.
In the high-level synthesis stage, previous works only consider the influence of clock arrival times on register sharing, but they do not pay any attention to the influence of clock arrival times on functional unit sharing. As a result, extra functional units are often required during functional unit binding. Based on that observation, in this dissertation, we consider the influence of clock arrival times on both register sharing and functional unit sharing for the high-level synthesis of nonzero clock skew circuits. We propose an integer linear programming (ILP) to solve this problem. Our objective is to minimize the circuit area for working with the lower bound of the clock period. Compared with previous works, experimental results show that our approach can achieve the lower bound of the clock period with a smaller area overhead.
In the logic synthesis stage, conventional clock skew scheduling only focus on data paths, but a gated clock design includes both data paths and clock control paths. Based on that observation, in this dissertation, we propose an approach to perform the co-synthesis of data paths and clock control paths in a nonzero skew gated clock design. Our objective is to minimize the required inserted delay for working with the lower bound of the clock period (under clocking constraints of both data paths and clock control paths). Different from previous works, our approach can guarantee no clocking constraint violation in the presence of clock gating. Experimental results show our approach can effectively enhance the circuit speed with almost no penalty on the power consumption.

並列關鍵字

clock period minimization ； logic synthesis ； high-level synthesis ； minimum area overhead ； clock skew scheduling

參考文獻

[6] Y.P. Chen and D.F. Wong, "An Algorithm for Zero-Skew Clock Tree Routing With Buffer Insertion", Proc. of IEEE European Design and Test Conference, pp. 230–236, 1996.

[7] J.P. Fishburn, "Clock Skew Optimization", IEEE Transactions on Computers, vol. 39, no. 7, pp. 945—951, 1990.

[10] S.H. Huang and C.H. Cheng, "Minimum-Period Register Binding", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 28, no. 8, pp. 1265—1269, 2009.

[12] N. Min and S.O. Memik, "Early Planning for Clock Skew Scheduling During Register Binding", Proc. of IEEE/ACM Design Automation Conference, pp. 429—434, 2007.

[13] T. Obata and M. Kaneko, "Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis", Proc. of IEEE International Symposium on Circuits and Systems, pp. 1521—1524, 2009.