透過您的圖書館登入
IP:3.137.222.30
  • 學位論文

支援DVB-T協定之雙路徑記憶體架構的快速傅立葉轉換器

Two Port Memory-based FFT Architecture for DVB-T

指導教授 : 陳元賀

摘要


正交分頻多工器OFDM(Orthogonal Frequency Division Multiplexing)技術在現在通訊系統中的廣泛應用,也是最常被拿來使用的調變技術,如: ADSL、DVB、802.11a等等。接著由硬體實現透過快速傅立葉轉換與反快速傅立葉轉換(Fast Fourier Transform, FFT/ Inverse Fast Fourier Transform, IFFT)來達到調變與解調變的目的。而快速傅立葉轉換所扮演的角色越來越重要,其應用於數位訊號處理、雷達、醫學電子等領域。隨著應用領域的擴展以及應用需求的深化,FFT處理器需要處理的點數也相應不同,針對不同的系統標準而有不同的點數規範,在這篇論文中,論述分析了幾種快速傅立葉轉換演算法的複雜性及其硬體架構設計。在傳統的架構中,它可分為管線式(Pipeline)和記憶體式(Memory-based)兩種架構,管線式有更高的吞吐量(Throughput)和控制單元簡單之優點,但其硬體面積較大;而記憶體式架構則反之。 本論文提出一個雙路徑記憶體式快速傅立葉處理器,此處理器以Radix-2快速傅立葉處理器為主,並找出一個記憶體存取的排程方法使其兩筆輸入資料在雙路徑模式中可並存運作,在依其運算過程的要求使其存入記憶體位置的時間和值皆為正確,在存入記憶體的過程中,因其運算過程中每個Stage所產生的Bit size 有增加情形,在此我們對其進行Dynamic Scaling的動作以利所需的存取的記憶體Bit Size要求降低,另外文中還有針對其旋轉因子(Twiddle Factor)進行研究,利用數學上的函數關係取其對稱性、量化以及誤差補償的方法減少ROM Size,最後整個架構可以支援DVB-T協定2K/8K FFT Point且其SNR可達到40dB以上。

並列摘要


Orthogonal frequency division multiplexer (OFDM) is used widely in communications systems now and modulation technique is also be used usually, such as ADSL, DVB, 802.11a etc. To achieve the purpose of modulation and demodulation, the Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) are implemented into a circuit. The FFT plays significant role in applying digital signal processing, radar, medical electronics, and other fields. With the expansion of application fields as well as the deepening of application requirements, FFT processor data points need to be addressed in different way standards for different systems have different points specification. It discusses to analysis several of FFT’s algorithm complexity and hardware architecture design algorithm in this paper. In traditional architecture, it can be divided into two architectures pipeline and memory-based. The advantages of pipeline have higher throughput rate and simple control unit, but it’s hardware larger more; otherwise memory-based has small area but low throughout rate compared with pipeline architecture. This paper proposes a two port memory-based FFT architecture. This processor is Radix-2 FFT processor and proposes a memory read and write method to make the two ports input data path mode operating. According to require of the computing process make its time and the value in the memory locations be all correct. In the process of the memory stored, because of the operation process for each stage produced of bit size had increase. Therefore, we do dynamic scaling to reduce request of memory access of bit size. In addition, we also research for twiddle factor, and make use of a function in math symmetrical, quantization and differential compensation to reduce ROM size. Finally, the architecture can support to DVB-T 2K/8K FFT point and can reach higher than 40dB in SNR.

並列關鍵字

FFT Memory based twiddle factor

參考文獻


[1] X. J. Li and Z. S. Lai, “A Low Power and Small Area FFT Processor for OFDM Demodulator,” IEEE Trans. Consumer Electron., vol. 53, no. 2, pp. 274-277, May. 2007.
[3] K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. New York: Wiley, 1999.
[4] Asymmetric Digital Subscriber Line Transceivers 2 (ADSL2), ITU-T Standard G.992.3, Jan. 2005.
[5] Very-High-Bit-Rate Digital Subscriber Line Transceiver 2(VDSL2), ITUT Standard G.993.2, Feb. 2006
[6] The Wireless LAN Media Access Control (MAC) and Physical Layer (PHY) Specifications, IEEE Standard 802.11, 1999.

延伸閱讀