透過您的圖書館登入
IP:18.191.174.168
  • 學位論文

動態隨機存取記憶體之刷新技術研究

Study on Refresh Techniques for DRAM Refresh Power Reduction

指導教授 : 鄭維凱

摘要


動態隨機存取記憶體(Dynamic Random Access Memory)有高效能以及低成本的特性,但是DRAM需要定期刷新(DRAM Refresh)的動作來維持資料的正確性,然而刷新會導致額外的能源耗損以及延遲記憶體存取而造成效能低落。隨著DRAM的容量增加,刷新所需的時間亦隨之增加,而導致刷新額外耗損變得不可忽略。 本論文中,我們觀察到資料保存時間(Retention Time)決定了刷新區間(tREFI),而實際上,並不是所有的DRAM Cell的資料保存時間都相同和需要相同的刷新區間,因此我們提出資料保存時間導向刷新技術以減少不必要的刷新,將DRAM內建的自動刷新(Auto Refresh)以不同精細度的刷新方式進行記憶體刷新,並於三種不同的刷新方法(All-bank, Per-bank, Partial-bank Refresh)上應用此技術,其中Partial-bank Refresh為本篇論文提出的一種新穎的刷新方法。我們由實驗結果證明,在這種有效率的刷新機制下能夠有效地減少大多數不必要的刷新,無論是對於刷新的額外耗損以及效能的提升都有顯著的幫助。

並列摘要


DRAM circuit requires periodic refresh operations to prevent data loss. However, DRAM refresh incurs extra power consumption and degrades system performance due to delaying of memory requests service. As DRAM density increases, DRAM refresh overhead is even worsen due to the increase of refresh cycle time. Therefore, refresh overhead is a noticeable issue. In this thesis, our key observation is that refresh interval(tREFI) is specified by retention time(tRET). In fact, not all cells have same retention time and need refresh operations at same period. To address this problem, we propose a retention-aware auto-refresh (RAAR) technique by all-bank, partial-bank, and per-bank refresh mode. Most unnecessary refresh operations are reduced by RAAR according to DRAM cells’ retention time. Experimental results show that our RAAR technique not only reduce refresh power effectively, but also improve memory access performance.

並列關鍵字

DDRAM DRAM refresh Power reduction

參考文獻


[1]W. Shin; J. Choi, J. Jang, J. Suh, Y. Moon, Y. Kwon, L-S. Kim, “DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing”, vol.65, no.10, pp.3207-3040, 2016.
[5]K. K. Chang, D. Lee, Z. Chishti, A. R. Alameldeen, C. Wilkerson and Y. Kim, O. Mutlu, “Improving DRAM Performance by Parallelizing Refreshes with Accesses” , IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), pp.356-367, 2014.
[8]I. Bhati M-T. Chang, Z. Chishti, S-L. Lu, B. Jacob, “DRAM Refresh Mechanisms, Penalties, and Trade-Offs”, IEEE Transactions on Computers, vol.65 no.1, pp.108-121, 2016.
[11]Y-H. Gong, S. W. Chun, “Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-power Refresh”, IEEE Transactions on Computers, vol.65, no.5, pp.1507-1517, 2016.
[12]I. Bhati, Z. Chishti, S-L. Lu, B. Jacob, “Flexible Auto-Refresh: Enabling Scalable and Energy-Efficient DRAM Refresh Reductions”, ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), pp.235-246, 2015.

延伸閱讀