在WCDMA下使用FPGA設計與合成於數位中頻降頻器

FPGA design and synthesis for digital down converter of WCDMA

黃國榮(Kuo-Jung Huang)

指導教授 ： 王瑞騰

國立暨南國際大學/科技學院/電機工程學系/碩士(2007年)

摘要

本論文以軟體定義無線電（Software Defined Radio），去實現適用於WCDMA系統之數位中頻降頻器。而數位中頻降頻器包含了許多元件，有數位數值震盪器（NCO），是以LUT方法來實現，可擁有較快處理速度。而CIC濾波器，是ㄧ個有彈性且免乘法器的濾波器。而FIR濾波器是以分散式算術法則來實現，它可節省面積且增加處理速度。最後以Verilog硬體描述語言完成硬體RTL設計，並使用ModelSim作時序驗證，再將電路合成，以完成WCDMA數位中頻降頻器。

關鍵字

軟體定義無線電 ； 數位中頻降頻器 ； Verilog硬體描述語言

並列摘要

In this paper, we present a digital IF down converter architecture for a W-CDMA terminal based on the software defined radio. Digital IF down converter includes many elements. There are NCO, the CIC filter, and the FIR filter. First, the NCO is implemented in the method of LUT and it could have higher speed. Second, CIC filter is a flexible and multiplier-free filter suitable for hardware implementation. Third, the FIR filter is implemented in the method of Distributed Arithmetic Algorithm that can save area and increase handling speed. Finally, we adopt hardware description language Verilog HDL for RTL design and using ModelSim software to accomplish timing verification; therefore, we can logic synthesis and then complete digital IF down converter design.

並列關鍵字

Software Defined Radio ； Digital IF Down Converter ； Verilog HDL

參考文獻

[1] TIM HENTSCHEL, MATTHIAS HENKER “The Digital Front-End of Software Radio Terminals”IEEE Pcrsonal Communications, August 1999

[2] Enrico Buracchini,“The Software Radio Concept”, IEEE Communications Magazinc September 2000.

[3] Miyeon Kim and Seungjun Lee, “Design of Dual-Mode Digital Down Converter for WCDMA and cdma2000” ETRI Journal, Volume 26, Number 6, December 2004

[4] Ming Jian, Weng Ho Yung, Bai Songrong, “An Efficient IF Architecture for Dual-Mode GSM/W-CDMA Receiver of a Software Radio” 1999 IEEE

[5] Won-Cheol Lee, Woon-Yong “Implementation of SDR-Based Digital IF for Multi-Band W-CDMA Transceiver” IEICE TRANS. COMMUM. October 2004