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  • 學位論文

超頻寬低雜訊放大器、W-Band升頻混波器及電容式開關數位類比轉換器之研究

Study of UWB LNA、W-Band Up-conversion Mixer and Switched-Capacitor DAC

指導教授 : 林佑昇
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摘要


本論文以操作在3~10GHz(Ultra-Wideband)之低雜訊放大器,及W-Band之升頻混波器,還有電容式開關數位類比轉換器之研究為目標,研究主題分為以下三個部分: 首先我們使用台積電0.18μm CMOS製程設計了一個低雜訊、高增益的寬頻放大器(3~10GHz),我們使用了LC並聯來達到提高增益的效果。在3~10GHz頻帶下有平坦的增益S21為11.2 ± 1.5 dB,雜訊指數為3.5±1 dB ,而IIP3 在6GHz時為-10dBm,電路消耗之功率為10.5mW,晶片大小為0.67mm2。 第二部份為一應用於77~81 GHz短距離汽車雷達之具有高增益及高隔離度的CMOS升頻混波器,以台積電90nm製程為基準設計。此升頻混波器包括: 一雙平衡式吉伯特單元;其含電流注入和雙負電阻補償技術,分別用於降低功率損耗及提升轉換增益、瑪遜巴倫(Marchand Balun)用於將LO輸入訊號由單端轉雙端及將RF輸出訊號由雙端轉單端。模擬結果表示此含有雙負電阻補償技術之CMOS升頻混波器應用於 W-Band頻帶射頻積體電路非常具有前景。 第三部分為一個應用在三角積分數位類比轉換器中重建濾波器的電容式開關數位類比轉換器,使用直接電壓轉換的切換式電容技術可以減少雜訊和元件布匹配的影響而不增加功率消耗,最後將前級的數位電路所輸出的15個的數位訊號,還原成類比訊號,此研究由台積電0.35μm製程設計。

並列摘要


In this thesis, operating in 3 ~ 10GHz (Ultra-Wideband) low noise amplifier(LNA), and W-Band Up-conversion Mixers, and Digital to Analog Converters using capacitive switches research , research themes are divided into the following three parts: First, we use the TSMC 0.18μm CMOS process design of a low-noise, high-gain broadband amplifier (3 ~ 10GHz), we use the LC parallel to achieve the effect of increasing the gain. In 3 ~ 10GHz band has a flat gain S21 was 11.2 ± 1.5 dB, noise figure of 3.5 ± 1 dB, and IIP3 in the 6GHz was-10dBm, the circuit's power consumption is 10.5mW, the chip size is 0.67mm2. In the second section, a TSMC 90nm CMOS up-conversion mixer with high CG and excellent LO-RF isolation for 77~81 GHz short range automotive radar is reported. The mixer comprises an enhanced double-balanced Gilbert cell with current injection for power consumption reduction, and dual negative resistance compensation for conversion gain (CG) enhancement, a Marchand Balun for converting the single LO input signal to differential signal, and another Marchand Balun for converting the differential RF output signal to single signal. The measured result indicates that the proposed up-conversion mixer with dual negative resistance compensation is promising for W-band RFIC applications. The third part is an application of the delta-sigma Digital to Analog Converter reconstruction filter using Switched-Capacitor Digital to Analog Converter, having direct voltage converter switched capacitor technology can reduce the noise impact of cloth and matching components without increasing power consumption Finally, the 15's digital signal output from the previous stage of digital circuits, reduced to an analog signal, this study was conducted by TSMC 0.35μm process design.

參考文獻


[1]林佑昇,邱弘緯,梁效彬 編著(2011): RFID 晶片設計。
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