奈米壓印製作橋接式多晶矽薄膜電晶體研究

Study on Fabrication of Bridged-Grain Poly-Si Thin-Film-Transistors with Nanoimprint Technology

黃品惇(Pin-Tun Huang)

指導教授 ： 陳建亨

國立暨南國際大學/科技學院/電機工程學系/碩士(2014年)

摘要

本論文研究製作橋接式多晶矽薄膜電晶體，先利用奈米壓印與離子佈植製作通道的間隔摻雜，再進行傳統多晶矽薄膜電晶體的製作，最後進行量測，了解通道摻雜對於元件特性的影響。
我們成功運用於奈米壓印在多晶矽上製作出線寬/間距約為400nm/800nm的分區摻雜結構，成功整合奈米壓印技術與傳統薄膜電晶體製程，製作出橋接式多晶矽薄膜電晶體，並由實驗結果發現，該電晶體展現出較高的開關電流比，較低的臨界電壓，和更為陡峭的次臨界擺幅，並藉由通道分區摻雜濃度的不同觀察對元件電性的影響，未來將應用在低成本高效能的薄膜電晶體應用上。

關鍵字

奈米壓印,橋接式,薄膜電晶體

並列摘要

In this thesis, we focus on the study of polycrystalline-silicon thin-film-transistors with bridged-grain channels fabricated using nanoimprint lithography. The grating doping regions in channel were fabricated by ion implantation through the PMMA, patterned with thermal nanoimprint lithography. Then the thin-film-transistors were fabricated by the conventional TFTs process. Finally, the electrical characteristics of proposed TFTs were investigated.
In our results, the bridged-grain poly-Si TFTs with 400/800 nm grating channels structure were fabricated successfully. The proposed poly-Si TFTs show lower threshold voltage, higher ON/OFF ratio, better subthreshold swing, higher field-effective mobility, and higher drain current than that with a conventional channel. This technique will be suitable for the fabrication of high-performance poly-Si TFTs at low cost in the future.

並列關鍵字

nanoimprint, bridged-grain, thin-film-transistor

參考文獻

[1] S D Brotherton, “TOPICAL REVIEW Polycrystalline silicon thin film transistors,” Semicond. Sci. Technol. 10 (1995) 721-738.

[2] Zhiguo Meng, Mingxiang Wang, and Man Wong, " High Performance Low Temperature Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin Film Transistors for System-on-Panel Applications," Transactions on electron devices, vol. 47, no. 2, pp. 404-409.

[3]R. E. Proano, R. S. Misage, and D. G. Ast, “Development and Electrical Properties of Undoped Polycrystalline Silicon Thin-Film Transistors”, Transactions on electron devices, Vol. 36, No. 9, pp. 1915-1922

[4]M.-K. Ryu, J.-Y. Kwon, and K.-B. Kim, "Solid Phase Crystallization(SPC) Behavior of Amorphous Si Bilayer Films With Different Concentration of Oxygen," Mat. Res. Mat. Soc. Symp. Rroc., vol. 6, pp. Q6.3.1-Q6.3.6, 2000.

[5]J. H. Choi, J. H. Cheon, S. K. Kim, and J. Jang, "Giant-grain silicon(GGS) and its application to stable thin-film transistor," Displays, vol. 26, pp. 137-142, 2005.