圖形化通道摻雜之橋接多晶矽 薄膜電晶體研究

Study of Bridged-Grain Poly-Si Thin-Film-Transistors with Patterned-Channel Doping

施璇(Syuan-Shih)

指導教授 ： 陳建亨

國立暨南國際大學/科技學院/電機工程學系/碩士(2016年)

摘要

此論文致力於製作不同的橋接多晶矽薄膜電晶體，首先利用奈米壓印技術製作出有不同線寬及圖案的橋接多晶矽電晶體，來研究不同圖案的摻雜對元件特性的影響。 我們成功利用了熱壓印製作出三種圖形(點、線、虛線)；兩種線寬(400/400nm、400/800nm)在多晶矽薄膜上作分區摻雜的結構，並用兩種不同的佈值劑量(1x〖10〗^15、2x〖10〗^15ions/〖"cm" 〗^2)和退火方式(RTP/MWA)去比較元件特性。 由實驗結果發現，有摻雜分區通道的橋接多晶矽薄膜電晶體展現出較高的開關電流比，較低的臨界電壓，和更為陡峭的次臨界擺幅，並藉由通道分區摻雜圖形的不同觀察對元件電性的影響，未來將應用在低成本高效能的薄膜電晶體應用上。

關鍵字

奈米壓印 ； 橋接式 ； 薄膜電晶體

並列摘要

In this thesis, we focus on the study of bridged-grain polycrystalline-silicon thin-film-transistors with patterned-channel doping. The patterned doping regions in channel were fabricated by ion implantation through the PMMA, patterned with thermal nanoimprint lithography. Then the thin-film-transistors were fabricated by the conventional TFTs process. Finally, the electrical characteristics of proposed TFTs were investigated.
In our results, the bridged-grain Poly-Si TFTs with 400/800 and 400/400 nm patterned-channel structures in all patterns (dot, line, dash) were fabricated successfully. The proposed Poly-Si TFTs show lower threshold voltage, higher ON/OFF ratio, better subthreshold swing, higher field-effective mobility, and higher drain current than that with a conventional channel. This technique will be suitable for the fabrication of high-performance poly-Si TFTs at low cost in the future.

並列關鍵字

Nanoimprint ； bridged-grain ； thin-film-transistor

參考文獻

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