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  • 學位論文

單指令集結構異質多核心上的線上多執行緒工作效能

Single-ISA Heterogeneous Multi-Core Architectures for On-Line Multithreaded Workload Performance

指導教授 : 杜迪榕
共同指導教授 : 陳依蓉(Yi-Jung Chen)

摘要


為了減少處理器能源的消耗及提升整體系統的效能,近年來有學者提出了單指令集異質多核心結構系統(Single-ISA heterogeneous architecture)。本研究針對單指令集結構異質多核心系統,提出線上(on-line)工作排班演算法,意即在不知道工作順序與時間的狀態下,動態的分配不同的零散的工作。不同於之前的研究只考慮如何減少能源的消耗,或如何增加工作的效能,本研究同時考量能源的消耗及工作的效能。實驗數據顯示,當針對耗能作選擇時,本研究提出的演算法耗能平均只有最佳排班的狀況下的一點零七倍。當針對效能作選擇時,本研究提出的演算法之執行時間平均只有最佳排班狀況下的一點零四倍,而在針對耗能-延遲時間作選擇時,本研究提出的演算法之「耗能-延遲時間乘積」平均只有最佳排班的狀況下的一點一四倍。

並列摘要


The single-ISA heterogeneous multi-core architecture has been proposed to reduce processor power dissipation and improve overall system performance. This work targets the single-ISA heterogeneous multi-core architecture, and proposes an on-line task scheduling algorithm that dynamically assigns independent sporadic tasks in the system. Different from previous works that schedule tasks to minimize power consumption or maximize performance only, the proposed on-line task scheduling algorithm considers performance and power consumption at the same time. The experimental results show that: 1. When the demand is energy, the energy consumption of our algorithm has 1.07 times over the algorithm that has oracle information on the average. 2. When the demand is performance, the execution time of our algorithm has only 1.04 times over the algorithm that has oracle information. 3. When the demand is energy-delay product, our algorithm has only 1.14 times over the algorithm that has oracle information and achieves the best results on the average.

參考文獻


[1] Alpha 21064 and Alpha 21064A: Hardware Reference Manual, Digital Equipment Corporation, 1992.
[2] Alpha 21164 Microprocessor: Hardware Reference Manual, Digital Equipment Corporation, 1998.
[3] Alpha 21264/EV6 Microprocessor: Hardware Reference Manual, Compaq Corporation, 1998.
[4] M. Becchi and P. Crowley, “Dynamic thread assignment on heterogeneous multiprocessor architectures.” In: Proceedings of the 3rd Conference on Computing Frontiers, 2006, pp. 29–40.
[5] J. Chen and L. John, “Efficient program scheduling for heterogeneous multi-core processors.” In: Proceedings of the 46th Annual Design Automation Conference, ser. DAC ’09. New York, NY, USA: ACM, July 2009, pp. 927–930.

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