應用於智慧型感測器之低成本電容式感測技術

Low Cost Capacitive Sensing Scheme for Smart Sensor

徐偉宏(Wei-Hung Hsu)

指導教授 ： 許孟烈

國立暨南國際大學/科技學院/電機工程學系/博士(2012年)

https://doi.org/10.6837/NCNU.2012.00113

摘要

本論文提出用於低成本智慧型感測系統的電容式感測技術，並且使用互補金氧半導體(CMOS)的製程技術來實現。研究目的是為了瞭解電容式感測讀取電路在標準CMOS技術實現下，在盡可能降低設計成本後所能得到的系統效能及限制。
首先在低功耗的前提下，利用定電流積分感測電容產生調變電壓，透過比較器和一些邏輯電路把電壓訊號轉換成半數位訊號，便於透過計數器轉換成數位值。這樣子的讀取電路消耗功率小於18?W、線性度優於1%、同時面積僅占了50?50?m2的大小，非常適用於陣列型態的感測電路。
接著為了實現低功耗和低電路複雜度的讀取電路，並進一步穩定電路，吾人提出新穎的電容比值調變電流 (CRMC) 設計技術，採用單級的電壓緩衝器來調變感測電容並得到對應的電流值。配搭積分的技巧將電流轉成脈波寬度調變 (PWM) 的輸出，有利於抵抗雜訊以及透過計數器轉換成數位值。
使用所提出的CRMC，吾人以0.35-μm 2P4M CMOS 製程實現三種因應不同電容感測器組態的電容式讀取電路。在3V 的供應電壓下，讀取電路的動態範圍可以達到7.9-bit到9.3-bit的範圍、線性誤差均可小於1%、最大的消耗功率為231 μW、取樣率可以達到數kHz甚至於數十kHz，足夠應付大多數的電容式感測訊號物理量的變動，也能夠有效降低智慧型感測器的成本。

關鍵字

互補金氧半導體 ； 脈波寬度調變 ； 電容式感測器 ； 電容式感測技術 ； 低成本 ； 智慧型感測器

並列摘要

This dissertation presents a study of low cost capacitive sensing scheme for smart sensor. For the implementation by standard CMOS process, we are engaged to investigate the performance of the capacitive interface circuit under low cost constraints.
For low power perspective, the sensing element is charged by a constant current to generate a modulation voltage, which is then converted to a quasi-digital signal by a comparator and peripheral logic circuits. The quasi-digital signal can be digitized by a counter. The whole interface circuit only consumes 18?W, with linearity error less than 1% and area occupation of 50?50?m2, which is very suitable for sensor array.
To further stabilize the interface circuit, we propose a low power and low circuit complexity sensing scheme, called capacitance-ratio-modulated current (CRMC), which is realized by a single-amplifier-based voltage buffer. The novel CRMC can modulate the sensing element as current. Through dual-slope integration technique, the CRMC can be converted to pulse width modulation (PWM) signal.
We implement three capacitive interface circuits based on the proposed CRMC by 0.35-μm 2P4M CMOS technology. The performance of these interface circuits can achieve linearity performance up to 1% and a dynamic range (DR) between 9.3 bits and 7.9 bits, with the highest power dissipation less than 231 μW and sampling rate up to several tens of kilo Hz at 3V supply voltage. These interface circuits can be further developed in low cost smart sensors for a wide application range.

並列關鍵字

Complementary Metal Oxide Semiconductor (CMOS) ； Pulse-width modulation ； Capacitive sensor ； Capacitive sensing scheme ； Low cost ； Smart sesor

參考文獻

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