利用原子層沉積製作氧化鋅薄膜電晶體之研究

Study on Zinc Oxide Thin-Film Transistors Fabricated by Atomic Layer Deposition

江承育(Cheng-Yu Chiang)

指導教授 ： 陳建亨

國立暨南國際大學/科技學院/電機工程學系/碩士(2014年)

https://doi.org/10.6837/NCNU.2014.00146

摘要

本論文利用原子層沉積法製作氧化鋅薄膜電晶體，探討在低溫電漿輔助原子層沉積之氧化鋅薄膜，經不同方式退火後的電性及物性，並配合奈米壓印技術製作3D類鰭狀氧化鋅薄膜電晶體，討論不同類鰭狀通道結構對元件特性之影響。
實驗結果顯示使用電漿輔助沉積之氧化鋅薄膜退火之後具有較強的(002)晶面優先取向。製程結束後在反應腔體內通氧氣退火250℃，15分鐘，完成後取出再以平板加熱器退火350℃，60分鐘之氧化鋅薄膜所製成之傳統薄膜電晶體，有最大的電流開關比(1.02×106)，載子移動率(5.39 cm2/V．s) 及最小次臨界擺幅(1.08 V/dec)。而3D類鰭狀氧化鋅薄膜電晶體方面，類鰭狀結構線寬/間距比較小之電晶體具最佳之特性，電流開關比可提升至1.81×106，載子移動率能提升至6.96 cm2/V．s，次臨界擺幅減小至0.78V/dec。本研究之結果，將可運用在未來平面顯示器應用上。

關鍵字

原子層沉積 ； 半導體薄膜 ； 薄膜電晶體

並列摘要

In this thesis, the ZnO TFTs with finlike channels were fabricated by atomic layer deposition and nanoimprint technology. The electrical and material characterizations of ZnO thin film fabricated by plasma-assisted atomic layer deposition in low temperature then thermal annealing were studied.
The preferred (002) peak orientation were improved in this study. The ZnO TFTs after in situ O2 annealing at temperature of 250℃, for 15 minutes then using hot plate annealing at temperature of 350℃, for 60 minutes, exhibits the largest on/off ratio(1.02×106), highest mobility(5.39 cm2/V．s), and sharpest subthreshold swing (1.08 V/dec) then other samples. The performance of ZnO finlike TFTs can be optimized by increasing the width/space ratio (l/s) of finlike structures. The ZnO finlike TFTs exhibits the higer on/off ratio(1.81×106), mobility(6.96 cm2/V．s), and sharper subthreshold swing (0.78 V/dec) The results of this study can be fabricated for the future flat-panel display applications.

並列關鍵字

atomic layer deposition ； semiconductor film ； thin-film transistors

參考文獻

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