整合三維堆疊混合記憶體之多核心系統晶片之溫度感知效能最佳化記憶體系統架構設計自動化方法

Thermal-Aware Memory System Design Automation Method for Multi-Processor System-on-Chips with 3D-Stacked Hybrid Memories

劉佳音(Chia-Yin Liu)

指導教授 ： 陳依蓉

國立暨南國際大學/科技學院/資訊工程學系/碩士(2018年)

摘要

利用穿矽通孔將不同資料儲存密度、存取速度、及平均存取功耗表現之不同記憶體，以垂直方式與多核心系統晶片整合，被視為可解決其記憶體頻寬需求問題的方法之一。然而，此三維堆疊方式會造成耗能密度增加，使晶片較易有過熱問題。多核心系統晶片整合三維堆疊記憶體架構之系統最高溫度來自於各堆疊晶片上的行為與硬體元件之間相互影響，包含處理軟體工作、記憶體存取、硬體元件配置與使用。而針對不同的應用程式組行為，所需之最佳硬體元件配置也不同；因此，為達最佳之系統溫度控制，應協力進行資料及工作配置與硬體元件配置。在此論文中，我們提出第一個考量系統溫度與資源限制，根據系統之應用程式組行為需求，決定最佳之記憶體系統資源分配設計自動化方法。我們考量堆疊SRAM 與 DRAM 之不同行為、選用 DRAM 時需佔用晶片層資源實作之記憶體控制器配置、及穿矽通孔之數量與位置之配置，並分析應用程式組的工作行為、資料存取行為及不同硬體元件的特性，設計出一符合系統溫度限制下之最佳化效能之記憶體系統組態。實驗結果顯示，與單純使用溫度感知資料及工作配置方法相比，我們的方法可在溫度限制下找到一記憶體系統組態，並最佳化其效能。

關鍵字

三維堆疊 ； 多核心系統晶片 ； 系統層設計自動化 ； 溫度問題 ； 混合記憶體架構

並列摘要

Stacking memories on Multi-Processor System-on-Chips (MPSoCs) by ThroughSilicon Vias (TSVs) provides high speed and wide bandwidth, and supplies heterogeneous integration. However, it is prone to face a thermal problem because of the stacked power density. In terms of the resource allocation, using stacked-DRAM and TSVs bundles occupies areas in the logic layer, which can be traded for local memories to improve performance. In this paper, we propose a thermal-aware hardware and software co-design synthesis algorithm to optimize the performance in the limited resources under thermal constraint. We consider stacked SRAM/DRAM, allocation of DRAM memory controllers(DMCs), configuration of TSV bundles, placement of local memories, and thermal-aware task and data co-allocation. Compared to stacked-SRAM and stacked-DRAM configuration, applying thermal-aware software-only method, the proposed method can achieve 149% and 138% performance improvement on the average. The system temperature are all well kept under the given thermal constraint, 85◦C

並列關鍵字

Thermal-aware Design ； Task and Data Co-allocation ； MPSoCs ； 3D-stacked Memories ； Design Automation Method

參考文獻

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