使用標準互補式金氧半導體製程之高性能電壓控制環形震盪器

High Performance Voltage-Controlled Ring Oscillators in Standard CMOS Process

刁宥升(Yu-Sheng Tiao)

指導教授 ： 許孟烈

國立暨南國際大學/科技學院/電機工程學系/博士(2011年)

摘要

本論文提出一個高性能的互補金氧半導體(CMOS)壓控環型震盪器(VCRO)的研究，目的是為了瞭解VCRO在標準CMOS技術實現下，應用在多個GHz時的限制。為了實現低電壓和寬調諧範圍的VCRO，吾人提出新穎的差動延遲震盪器設計技術，採用互補電流控制來延伸控制電壓範圍以及操作頻率。互補電流控制可以擺脫傳統的VCRO控制電壓不能涵蓋整個供應電壓範圍的限制，當製程技術提升至奈米尺度，使得供應電壓下降低於1V時，互補電流控制技術將可以繼續被應用。
使用所提出的新差動延遲單元，吾人以0.18-μm 1P6M CMOS 製程實現一個採用三級架構和multiple-pass loop 技術的VCRO。在1.8V 的供應電壓下，VCRO可以達到寬調諧範圍以及高速操作。量測的結果顯示出全範圍控制電壓從0到1.8V時，操作頻率範圍從8.36到1.29-GHz。當供應電壓是1V時，全範圍控制電壓從0到1V時，操作頻率從4.09到0.479-GHz。量測中心頻率8.35-GHz在1-MHz偏移處的相位雜訊為-100.22dBc/Hz，FOM是-159.95dBc/Hz。當供應電壓是1V時，量測中心頻率4.09-GHz在1-MHz偏移處的相位雜訊是-94.22dBc/Hz，FOM是 -151.95dBc/Hz。不含PAD的晶片核心面積是106×76.2 μm2。藉著使用這些技術，也許可能延伸VCRO的應用到某些以前需要LC震盪器特性的領域。
此外，吾人亦設計一個可工作在1V電源與2.45-GHz的鎖相迴路(PLL)電路應用在微波2.45-GHz RFID 系統，PLL中的VCO使用四級的multiple-pass loop架構和吾人所提出的新延遲單元。PLL的模擬結果顯示，當供應電壓是1V時，操作頻率可達2.45-GHz，鎖定時間是25μs。

關鍵字

互補金氧半導體 ； 壓控震盪器 ； 環型壓控震盪器 ； 互補控制電流技術 ； 鎖相迴路 ； 高速 ； 低電壓 ； 寬諧調範圍.

並列摘要

This dissertation presents a study of high performance voltage controlled ring oscillators (VCRO) in standard CMOS process for multiple gigahertz applications. A differential delay cell with a novel complementary current control scheme is proposed for low-voltage and wide tuning-range VCROs. The proposed complementary current control scheme can extend the control voltage to cover the full-range of power supply voltage, which is unable to accomplish in a conventional VCRO. The full coverage of control voltage range not only widens the operation frequency range but also makes the circuit suitable for low-voltage operation. As the process technology is promoted to nanometer, the supply voltage drops below 1 V, the complementary current control scheme can continue to be applicable.
Using the proposed new differential delay cell, a voltage-controlled ring oscillator employing a three-stage structure and multiple-pass loop techniques, implemented in 0.18-μm 1P6M standard CMOS process, could achieve a wide tuning-range and very high-speed. Measured results for 1.8 V power supply show that a wide operation frequency range from 8.36-GHz to 1.29-GHz is accomplished for the full control voltage range of from 0 V to 1.8 V. The measured phase noise is -100.22 dBc/Hz at 1-MHz offset from the 8.35-GHz center frequency, and the figure of merit (FOM) is -159.95 dBc/Hz. When the supply voltage is reduced to 1 V, the operation frequency range is from 4.09-GHz to 0.479-GHz for the full control voltage range of from 0 V to 1 V. The measured phase noise is -94.22 dBc/Hz at 1-MHz offset from the 4.09-GHz center frequency, and the figure of merit (FOM) is -151.95 dBc/Hz. The chip core area without PAD is 106×76.2 μm2. By using these techniques, it may be possible to broaden the utilization of VCRO into some applications that previously required chip area consuming LC-tank oscillators.
Besides, for the application to microwave-band RFID system, we have designed a PLL employing the VCRO with the proposed new delay cell and the four-stage multiple-pass loop structure. The simulation of the PLL shows that when the supply voltage is 1 V and the operation frequency is 2.45-GHz, the lock time is 25 μs.

並列關鍵字

Complementary Metal Oxide Semiconductor (CMOS) ； Voltage-Controlled Oscillator (VCO) ； Voltage-Controlled Ring Oscillator (VCRO) ； Complementary Current Control Technology ； Phase-Locked Loop (PLL) ； High-Speed ； Low-Voltage ； Wide Tuning-Range.

參考文獻

[1] TSMC. (2001, NOVEMBER). TSMC Announces Industry's First 0.13-Micron Mixed-Signal/RF Test Chip [On line]. Available: http://www.marketwire.com/press-release/TSMC-Announces-Industrys-First-013-Micron-Mixed-Signal-RF-Test-Chip-481563.htm.

[2] Peter Vancorenland, Michiel S. J. Steyaert, “A 1.57-GHz fully integrated very low-phase noise quadrature VCO,” IEEE Journal of Solid-state Circuits, vol. 37, no. 5, pp. 653-656, May 2002.

[3] Marc Tiebout, Hans-Dieter Wohlmuth, Werner Simbürger, “A 1V 51-GHz fully-integrated VCO in 0.12μm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, vol. 1, CA, USA, February 2002, pp. 238-239.

[4] Seog Jun Lee, Beomsup Kim, Kwyro Lee, “A Novel High-speed Ring Oscillator for Multiphase Clock Generation Using Negative Skewed Delay Scheme,” IEEE Journal of Solid-state Circuits, vol. 32, no. 2, pp. 289-291, February 1997.

[5] Chan-Hong Park, Beomsup Kim, “A Low-Noise, 900-MHz VCO in 0.6-μm CMOS,” IEEE Journal of Solid-state Circuits, vol. 34, no. 5, pp. 586-591, MAY 1999.