應用於V頻帶互補式金氧半注入鎖定型除頻器及壓控振盪器之研製

Design of CMOS Injection-Locked Frequency Divider and Voltage-Controlled Oscillator in V-band Application

翁榆航(Yu-Hang Wong)

指導教授 ： 黃天偉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.01438

摘要

無線通訊技術不斷地蓬勃發展，射頻積體電路也朝向更高頻率、更寬頻及與基頻電路更高的整合度之趨勢發展。在現今的收發機中，一個穩定的信號源是不可或缺的，而鎖相迴路則時最常被使用的高品質信號源。
因此，高速鎖相迴路的設計成為一個嚴峻的挑戰。而在高速鎖相迴路中，壓控振盪器以及第一個除頻器的操作頻率都遠高於其餘，這兩個電路也成為設計高速鎖相迴路時的最重瓶頸。
本篇論文的目的是要設計且實現適合整合於V頻帶鎖相迴路系統的除頻器和壓控振盪器。其中除頻器的研究重心在於增加其鎖頻範圍、降低其直流功耗以及減小其晶片面積。壓控振盪器的研究重心則在於其頻率調整範圍和提高其效率。
在介紹過一些常用的除頻器架構之後，一個改良式變壓器回授的注入鎖定型除頻器將被介紹，此變壓器可以確實有效的提昇電壓振幅來提昇除頻器電路中混頻器部份的轉換增益。此除頻器的鎖頻範圍為50到62GHz，其功率消耗為10.8mW。而實現的壓控振盪器的效率則高達1.25，其頻率調整範圍大小為8.8%。
最後是一個不具有額外電壓控制或電感性增幅元件的注入鎖定型除頻器，其鎖頻範圍是由53到67GHz。其功率消耗在高偏壓模式下只有4mW，在低偏壓模式下只有1.2mW，在低偏壓模式下其鎖頻範圍仍有6GHz
以上所有電路都實現於0.13-um互補式金氧半導體製程。

關鍵字

鎖相迴路 ； 除頻器 ； 壓控震盪器 ； 注入鎖定

並列摘要

With the development of wireless communication technologies, RF integrated circuits move toward higher frequencies, wider bandwidth, and higher integration level with base-band circuits. A stable LO source is indispensable in modern transceiver. Phase-locked loop (PLL) is the most widely used high quality LO source.
Therefore, the research on high-speed phase-locked loop becomes an astringent challenge. Since the operating frequency of the voltage-controlled oscillator(VCO) and the first frequency divider (FD) is among all other building blocks in the PLL, they becomes the design bottleneck of high-speed PLL system.
The goal of this thesis is to design and implement FD and VCO suitable for integrated into V-band PLL system. The research of the FD focuses on improving the locking range at high frequency, decreasing the DC power consumption, and minimizing the chip size. The research of the VCO focuses on tuning range and efficiency.
After an introduction of several FD topologies, a modified injection-locked frequency divider (ILFD) with transformer feedback is designed and implemented. The transformer can effectively increase the voltage swing and so the conversion gain of the mixer in the FD is increased. The locking range of the FD is 50-to-62GHz and consumes 10.8mW. Then a V-band VCO is realized with high efficiency up to 1.25. and the tuning range is 8.8%.
Finally, an ILFD is designed without extra control-voltage of inductive peaking components. The locking range is from 53-to-67GHz. And the power consumption is only 4mW for high-supply-voltage mode and 1.2mW for low-supply-voltage mode. The locking range of the low-supply-voltage mode is still up to 6GHz.
All the circuits mentioned above are implemented in CMOS 0.13-um process.

並列關鍵字

PLL ； frequency divider ； VCO ； injection-locked

參考文獻

[1] Park, C. and T. S. Rappaport, “Short-range wireless communications for next-generation networks: UWB, 60 GHz millimeter wave WPAN, and ZigBee,” IEEE Wireless Communications, Vol. 14, 70–78, Aug. 2007.

[2] M. Devulder, et al. “60 GHz UWB Transmitter for Use in WLAN Communication” International Symposium on Signals, Systems and Electronics, pp 371-314, Jul. 2007

[3] Y.-H. Wong, W.-H Lin, ”A 50-to-62GHz Wide-Locking-Range CMOS Injection-locked Frequency Divider with Transformer Feedback,” IEEE Radio Frequency Integrated Circuit Conf., pp. 435-438, Jun. 2008.

[4] C. Lee, S.-L. Liu, “A 58.4-to-60.4GHz Frequency synthesizer in 90nm CMOS,” IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 196-197, Feb. 2007.

[6] J. Lee, B. Razavi, “A 40GHz Frequency Divider in 0.18-μm CMOS Technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.