奈米壓印技術製作奈米多通道SONOS 薄膜電晶體記憶體之研究

Fabrication of Multiple Nano-Channel SONOS TFTs Memories by Nano Imprint Technology

黃建仁(Chien-Jen Huang)

指導教授 ： 陳建亨

國立暨南國際大學/科技學院/電機工程學系/碩士(2010年)

摘要

本論文整合了UV奈米壓印技術與傳統薄膜電晶體製程，製作出奈米多通道SONOS薄膜電晶體記憶體，首先利用UV奈米壓印與反應性離子蝕刻的技術在多晶矽上製作出奈米多通道結構，再進行多晶矽SONOS薄膜電晶體記憶體的製作，並藉由HP-4156、HP-4284和Agilent B1500量測完成的SONOS記憶體元件來了解多通道結構的改變對於元件特性的影響。 實驗結果顯示，我們已成功製作出最小線寬/間距約為100nm/50nm之奈米壓印膜具，並運用於奈米壓印在多晶矽上製作出最小線寬/間距約為75nm/75nm的奈米多通道結構，成功地整合奈米壓印技術與傳統薄膜電晶體製程，製作出之奈米多通道薄膜電晶體，且由實驗結果發現，線寬100nm/間距100nm的奈米多通道結構的SONOS薄膜電晶體記憶體，展現出較高的開關電流比(~3.6×107)，較低的臨界電壓(~0.6V)，載子遷移率(~42 cm2/V-sec )，更為陡峭的次臨界擺幅(~270 mV/dec)及較大的記憶視窗和較快的寫入抹除速度，未來可將運用在平面顯示器的系統面板之應用上。

關鍵字

奈米壓印 ； SONOS ； 多通道 ； 薄膜電晶體

並列摘要

In this thesis, the multiple nano-channel SONOS thin film transistor memories were fabricated by combing UV nano imprint and conventional photolithography. The multiple nano-channels were fabricated by UV NIL and reactive ion etching. Then, the SONOS thin film transistor memories were fabricated. The electrical characteristics were measured by HP-4156, HP-4284, and Agilent B1500.
In our results, the mold with the line/space width of about 100/50 nm and the nano-channel with the line/space width of about 75/75 nm were both fabricated successfully. The SONOS TFT memories with multiple nano-channels have higher on/off ratio (~3.6×107), lower threshold voltage (~0.6V), higher mobility (~42cm2/V-sec), sharper sub-threshold swing (~270 mV/dec), larger memory window (1.7V), and faster program/erase efficiency than the SONOS TFT memories with the simple channels. This technique will be suitable for the future SOP applications of the flat panel display.

並列關鍵字

nano imprint ； SONOS ； multiple channel ； thin film transistor.

參考文獻

參考文獻

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