蕭特基矽奈米線快閃記憶體

Schottky Barrier Silicon Nanowire SONOS Flash Memory

章緯(Chang, Wei)

指導教授 ： 連振炘 ； 吳文發 ； 施君興

國立清華大學/電機資訊學院/電子工程研究所/博士(2011年)

摘要

隨著行動式電子產品的蓬勃發展使得非揮發性快閃記憶體近幾年的需求大幅的增加，然而隨著元件尺寸及閘氧層厚度日益縮小以及非揮發性快閃記憶體使用較高的操作電壓而使得非揮發性快閃記憶體面臨嚴峻的挑戰。因此，近幾年來矽奈米線Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)型式的非揮發性快閃記憶體便被提出用來取代傳統的SONOS型式的非揮發性快閃記憶體，並廣泛的應用於System-on-Chip (SOC)， System-on-Panel (SOP)，3D Integration Applications (3D IC)，以及未來元件的微縮上。針對目前非揮發性快閃記憶體所面臨的問題，因此本論文提出一個新穎的蕭特基矽奈米線電荷捕捉式快閃記憶體作為未來非揮發性快閃記憶體的解決方案，利用實際完成的矽奈米線快閃記憶體元件，針對元件在寫入、抹除、讀取等方面的操作方式，以及元件特性與可靠度等作一實際的量測與分析，藉此驗證此新穎蕭特基矽奈米快閃記憶體除符合傳統快閃記憶體的基本需求外，更能進一步提升快閃記憶體的元件特性並適合用於未來的非揮發性快閃記憶體。
本論文藉由蕭特基源/集極以增加在矽奈米線中的電場，在導入矽奈米線以及環狀閘極增加閘極的控制力，藉由此新穎的蕭特基矽奈米線結構，此一蕭特基矽奈米線非揮發性快閃記憶體可以擁有較低的操作電壓，再者，較低的操作電壓也使得蕭特基矽奈米線非揮發性快閃記憶體具有非常好的元件穩定性與可靠性。此外，利用蕭特基元件獨特的雙向導通的特性，可以使元件做區域性的寫入與抹除，藉此操作達到多位元的應用。在矽奈米線上，透過簡單的矽化物製程便能有效的降低快閃記憶體的操作電壓，以及提升其元件穩定性與可靠性，因此，此蕭特基矽奈米線快閃記憶體成為未來極具優勢的候選者。

關鍵字

蕭特基 ； 奈米線 ； 快閃記憶體

並列摘要

Silicon nanowire has attracted a growing interest from semiconductor industry to replace the bulk Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory in future cell scaling, system-on-chip, system-on-panel, and 3D integration applications. However, a relatively high gate voltage is still required for the conventional nanowire SONOS cell during programming or erasing. Aggressive scaling of operation voltage is much preferred to improve cell speed, energy dissipation, periphery circuitry, and cell reliability for the use in practical embedded or mobile applications. This dissertation presents an innovative Schottky barrier Silicon nanowire charge-trapping SONOS Flash memory cell, and performs a thorough study of its operations for use in future nonvolatile memory cell. Real silicon cell fabrications and in-depth measurements are performed to examine the programming, erasing and reading operations of this new memory cell incorporated with thermal retention and cycling reliability characterizations.
By applying Schottky barrier source/drain to enhance electrical field in silicon gate-all-around nanowire, the nonvolatile Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory can operate at a gate voltage of 5 to 7V for programming, and -7 to -9V for erasing through Fowler-Nordheim tunneling. The larger gate voltage is, the faster programming/erasing speed and wider threshold-voltage shift are attained. Importantly, the Schottky barrier nanowire SONOS cells exhibit superior 100K cycling endurance and high-temperature retention without any damages from metallic silicidation process or field-enhanced tunneling. In addition, a localized programing and erasing scheme can be utilized to enhance the threshold voltage shift window in this Schottky barrier nanowire SONOS cell. The breakthrough in low-voltage programming and erasing operations with simple silicidation process make the Schottky barrier silicon nanowire SONOS cell very promising in future 3D integration, system-on-chip, and system-on-panel applications.

並列關鍵字

Schottky Barrier ； Nanowire ； Flash Memory

參考文獻

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