非對稱蕭特基能障薄膜電晶體與浮停閘極記憶體元件之製作與特性分析

Fabrication and Characterizations of Asymmetric Schottky Barrier Thin-Film Transistors and Floating Gate Memory Devices

林歷樺(Li-Hua Lin)

指導教授 ： 林鴻志 ； 黃調元

國立交通大學/電機學院/電子工程系所/碩士(2011年)

https://doi.org/10.6842/NCTU.2011.00111

摘要

在本論文中，我們利用一種新穎且低成本的雙重微影成像技術成功地製作出非對稱蕭特基能障薄膜電晶體。這個方法需要利用I-line光學步進機進行兩次的微影曝光以及後續的蝕刻步驟來定義出實際的閘極圖案，這樣的一個方式不僅有機會將閘極長度微縮至奈米尺度而且還能將元件的源極/汲極接面製作成非對稱式結構。這個新穎的非對稱蕭特基能障薄膜電晶體在順向模式的操作下是以矽化鎳(NiSi)蕭特基接觸當作源極而磷離子摻雜區域當作汲極，如此一來可以明顯地降低漏電流並且有效地減緩雙極性導通的現象。除此之外，一個兩段式斜率的次臨界電流-電壓特性也被觀察到，電荷載子的注入機制在此將被分析解釋。當利用矽化鎳當作源極，我們將研究由於陡峭的能帶彎曲引發的源極端的熱電子注入現象。顯著的閘極電流以及負電阻現象可以同時被觀察到，這被認為是源極端產生的熱電子被注入氧化層並且動態地被陷補所致。
以這個獨特的非對稱蕭特基能障結構為基礎，我們也成功地製作並分析浮停閘結構的快閃記憶體元件。因為源極端具有陡峭蕭特基能障，因此可以誘發熱電子並且在低電壓操作下被高效率地由源極端注入浮停閘，這與傳統的汲極端熱電子注入是不同的。相較於傳統的薄膜電晶體浮停閘記憶體元件，非對稱蕭特基能障薄膜電晶體浮停閘元件在低電壓操作下展現了較高的寫入速度。

關鍵字

蕭特基能障 ； 雙重微影 ； 非對稱 ； 源極端熱電子注入 ； 浮停閘極

並列摘要

In this thesis, asymmetric Schottky barrier (ASSB) thin film transistors (TFTs) are successfully fabricated by utilizing a novel and low-cost double patterning technique. The method involves twice the lithography with an I-line stepper and subsequent etching process steps to define the real gate pattern, which is not only a promising scheme for achieving nanoscale gate length but also feasible for fabricating devices with asymmetric source/drain (S/D) junctions. The novel ASSB-TFT devices operated in forward mode featuring a NiSi Schottky contact at the source side and a phosphorous-doped drain can significantly lower leakage current and thus the ambipolar conduction is largely mitigated. Moreover, a two-step subthreshold transfer characteristic is also observed and the carrier injection mechanisms are analyzed.
When the NiSi layer is used as the source, the phenomenon of a source-side hot electron injection triggered by the sharp energy band bending is investigated. A large gate current and the negative-differential conductance (NDC) behavior are simultaneously observed, which is attributed to hot electron generated at the Schottky source side and dynamic hot electron trapping in the oxide.

Based on this unique ASSB structure, floating-gate (FG) device for Flash memory is also successfully fabricated and characterized. The sharp Schottky barrier at the source side can induce hot electrons, and it can be used to provide high injection efficiency at low voltage rather than conventional drain-side channel hot electron injection. Compared with a conventional TFT-FG memory device, the ASSB TFT-FG memory device exhibits high-speed programming at low voltage.

並列關鍵字

Schottky barrier ； double-patterning ； asymmetric ； sourc-side hot electron injection ； floating gate

參考文獻

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