低功耗 CMOS 分佈型低雜訊放大器及低損耗 CMOS 帶通濾波器之分析與設計

Analysis and Design of Low-Power CMOS Distributed Low-Noise Amplifiers and Low-Insertion-Loss CMOS Bandpass Filters

張錦法(Jin-Fa Chang)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/博士(2011年)

摘要

本論文主要以超寬頻系統(UWB)低功耗 CMOS 接收機前端、60 GHz低損耗 CMOS 帶通濾波器及60 GHz高效率功率放大器之分析與設計為研究目標。此論文的前半段，我們用CMOS製程技術，分析與實現了超低損耗傳輸線、直流~10.5 GHz低功耗分佈型低雜訊放大器和一些矩陣式低功耗分佈型低雜訊放大器。在論文的後半段，我們以CMOS製程技術實現了一些低功耗低雜訊放大器、低功耗高轉換增益接收機前端具有高止帶抑制特色、應用於V頻帶1.87 dB低介入損耗微型帶通濾波器與兩個有效傳輸零點和60 GHz 高效率功率放大器與威爾金森功率結合器。
首先，我們用0.18 μm CMOS製程技術來實現傳輸線電感器，並分析與模型化。在電感耦合電漿蝕刻(ICP)後，有顯著的改善了傳輸線電感器之參數：特徵阻抗 (ZO)、衰減常數 (α)、有效介電常數(εeff)、最小雜訊指數 (NFmin)、基板電容/ 電導 (C/G)、串聯電感/電阻(L/R)、Q 值(Q-factor)和最大功率轉移 (GAmax)。
第二部份，我們使用了0.18 μm CMOS製程技術並在閘極傳輸線端採用了推薦的電阻電容終端網路(RC terminal network)與140 Ω終端電阻實現了一個直流~10.5 GHz低功耗分佈型低雜訊放大器(取代了傳統的50 Ω終端電阻與近年來發表之電阻電感終端網路(RL terminal network))。量測結果顯示，除了低與平坦的雜訊指數(NF) 3.2±0.3 dB、高與平坦之功率增益(S21) 10.5±1.4 dB、群延遲變動 ±13.8 ps。與頻寬大於7.5 GHz 之CMOS 分散型放大器或低雜訊放大器比較，本電路有最佳的雜訊指數與相位線性度(phase linearity)。
第三部份，我們分析與設計了一些矩陣式低功耗、高功率增益與低雜訊CMOS分佈型放大器。用0.13 μm CMOS製程技術提出一個1×2矩陣型(一級)與一個2×2矩陣型(兩級) 分佈型放大器與電阻電感閘極終端(RL gate terminal)應用於超寬頻系統。在低雜訊模式下(LN)，2×2矩陣型分佈型放大器在3~10 GHz完成了平坦又高功率增益14.07±1.69 dB與2.8 dB之平均雜訊指數。在近期發表超寬頻系統之分佈型放大器或低雜訊放大器文獻中，本電路是最佳的雜訊指數之一。在低增益模式下(LG)，2×2矩陣型分佈型放大器在3~10 GHz完成了平坦又高功率增益11.03±0.98 dB與4.25 dB之平均雜訊指數。在近期發表超寬頻系統之CMOS分佈型放大器或低雜訊放大器文獻中，本電路是最低功耗之一。用0.18 μm CMOS製程技術提出一個使用雙電感補償串聯增益級之2×3矩陣型分佈型放大器，在0.3~10.5 GHz完成了功率增益24.5±1.5 dB與3.9 dB之平均雜訊指數。在近期發表超寬頻系統之分佈型放大器或低雜訊放大器文獻中，本電路是最佳的功率增益之一。我們再使用0.18 μm CMOS製程技術，改善與最佳化2×2矩陣型分佈型放大器之架構，完成一個1.2~8.6 GHz兩級分佈型放大器，串聯增益級為兩個增強型的CMOS反轉器所構成。使用多樣雜訊抑制技術，同時完成平坦與低雜訊指數、高功率增益。在低增益模式(LG)，完成一個1.2~8.6 GHz分佈型放大器、功率增益11.41±1.39 dB、平均雜訊指數3.74 dB與9.85 mW低功耗。在近期發表頻寬大於6.5 GHz、功率增益大於10 dB與平均雜訊指數低於4 dB之CMOS分佈型放大器或低雜訊放大器文獻中，本電路擁有最低功耗。
此論文的後半段，首先我們使用0.18 μm CMOS製程技術，提出一些低功耗、低雜訊放大器與低功耗接收機前端。第一個低雜訊放大器為一個2.76 mW、3~10 GHz共閘極(CG)低雜訊放大器。除了2.76 mW低功耗外，我們推薦一種新型匹配網路(取代傳統並聯電感器(只有LS1))與推薦補償電感器(LC 與 LD2 分別補償中頻與高頻功率增益之損耗)去增加輸入匹配頻寬與S21的頻寬。接下來，第二個低雜訊放大器，我們改良了2.76 mW、3~10 GHz共閘極低雜訊放大器，提出了輸入端T型匹配網路(T-match input network)與基底自偏壓(self-body-bias)技術完成了一個0.99 mW、3~10 GHz共閘極低雜訊放大器。當VG = 0.77 V時，低雜訊放大器消耗2.15 mW，可在3~10 GHz完成了完成輸入返回損耗為–10.4~ –35.5 dB、10.4 dB功率增益與平均雜訊指數4.9 dB。當VG = 0.63 V時，低雜訊放大器消耗0.99 mW，可在3~10 GHz完成了完成輸入返回損耗為–10.7~ –35.8 dB、7.9 dB功率增益與平均雜訊指數6 dB。在近期發表頻寬大於6 GHz之CMOS低雜訊放大器文獻中，本電路擁有最低功耗。第三個低雜訊放大器，我們改良了2.76 mW、3~10 GHz共閘極低雜訊放大器完成一個包含高止帶抑制濾波器(一個被動濾波器與一個主動濾波器)之3.2~9.7 GHz低功耗低雜訊放大器。量測結果顯示，多止帶抑制於0.9/1.8/2.4/17.6/19.5 GHz 時，分別為53.3/26.4/26.5/60/59.5 dB。除了功耗4.68 mW、功率增益10.8 dB、頻寬6.5 GHz、雜訊指數4.8 dB外，在直流~ 2.5 GHz與11.2~ 20 GHz兩個止帶，止帶抑制皆大於21.6 dB。然後我們提出一個3~9 GHz、9.45 mW、25.7±1.5 dB高增益與高止帶抑制之低功耗接收機前端包含四個有效傳輸零點。在低增益模式中(LG)，僅消耗9.45 mW完成了25.7±1.5 dB高轉換增益、6 GHz的頻寬、6.95 dB雜訊指數、–8 dBm三階交調截取點(IIP3)。此外，使用推薦的接收機前端架構，完成了隔離度LO-RF/ LO-IF/ RF-IF在低增益模式(LG)分別為–91.9/ –42.7/ –67.1 dB、在高增益模式(HG)分別為–95.6/ –37.9/ –65.9 dB。在近期發表轉換增益大於20 dB、頻寬大於6 GHz之CMOS接收機前端文獻中，本系統擁有最低之功耗 (據作著所知)。之後，我們改善了9.45 mW低功耗接收機前端，最佳化為一個可變增益低功耗CMOS接收機前端。推薦之接收機前端損耗7.2 mW完成了20.21±1.97 dB轉換增益、3.15 dB最低雜訊指數、–6 dBm三階交調截取點(IIP3)。據作著所知，在近期發表功耗低於10 mW之CMOS超寬頻系統接機前端文獻中，本系統擁有最低之雜訊指數。
接下來，我們使用0.13 μm CMOS製程技術提出了具有兩個有效傳輸零點應用於V頻帶(V-band) 1.87 dB低介入損耗之微型帶通濾波器，低於3 dB之介入損耗(1/S21)、輸入返回損耗與輸入返回損耗小於 –10 dB之頻寬為49.5~82.5 GHz。此推薦濾波器具兩個可調式的有效傳輸零點之特色：串聯電容(Cs)可調低頻傳輸零點、並聯電容(Cp)可調高頻傳輸零點。晶片面積僅為0.466x0.307 mm2, i.e. 0.143 mm2 (不含測試墊(pads))。
最後，我們使用90 nm CMOS製程技術使用提出一個60 GHz 高效能(高功率增益、高飽和輸出功率(Psat)、輸出1 dB壓縮點(OP1dB)、功率附加效率(PAE)) 功率放大器與威爾金森功率分配器/ 結合器

關鍵字

接收機前端 ； 低功耗 ； 低雜訊 ； 分佈型放大器 ； 低介入損耗 ； 帶通濾波器 ； 有效傳輸零點 ； 功率放大器 ； 矩陣式 ； 低雜訊放大器 ； V頻帶 ； 功率附加效率 ； 威爾金森功率分配器/ 結合器 ； 傳輸線電感器 ； 電感耦合電漿蝕刻 ； 閘極終端網路 ； 群延遲變動 ； 基底自偏壓技術 ； 多止帶抑制 ； 飽和輸出功率 ； 輸出1 dB壓縮點

並列摘要

This thesis focuses on the analysis and design of low-power CMOS receiver front-ends for ultra-wideband (UWB) systems, 60 GHz low-insertion-loss CMOS bandpass filters, and 60 GHz high efficiency power amplifier. In the first half of this thesis, we discuss the analysis and implementation of an ultra-low-loss transmission line, a low-power DC~10.5 GHz distributed low noise amplifier (DA), and a number of matrix low-power distributed low-noise amplifiers (LNAs) in the CMOS technology. In the second half of this thesis, the implementation of a number of low-power CMOS LNAs, low-power and high conversion gain receiver front-ends with high stop-band rejection feature, miniature 1.87 dB low-insertion-loss V-band bandpass filters with two finite transmission zeros, and a 60 GHz power amplifier with Wilkinson power combiner in the CMOS technology is explained.
First of all, transmission line (TL) inductors that we analyze and model, are implemented in 0.18 μm CMOS technology. Significant improvements in TL inductor parameters characteristic impedance ZO, attenuation constant α, effective permittivity εeff, minimum noise figure NFmin, substrate capacitance/conductance C/G, series inductance/resistance L/R, Q-factor, and GAmax are achieved after the CMOS-compatible inductively-coupled plasma (ICP) etching, which removes the silicon underneath the TL inductors.
Second, we implement a low power DC~10.5 GHz distributed low-noise amplifier that adopts the proposed RC terminal network with 140 Ω terminal resistance over the frequency band of interest (instead of the traditional 50 ? terminal resistance or the recently proposed RL terminal network) for the gate transmission line in the UWB pulse radio systems using standard 0.18 μm CMOS technology. This distributed LNA presented flat and low noise figure (NF) of 3.2±0.3 dB, flat and high power gain (S21) of 10.5±1.4 dB, and small group delay variation of ±13.8 ps. This is the best NF and phase linearity results ever reported for a CMOS DA or wideband LNA with bandwidth greater than 7.5 GHz.
Third, we analyze and design a group of matrix low power, high gain, and low-noise CMOS DAs. A 1×2 matrix (single-stage) and a 2×2 matrix (two-stage) test DAs for UWB systems are demonstrated with RL gate terminal in 0.13 μm CMOS technology. In low-noise (LN) mode, the 2×2 DA achieved flat and high S21 of 14.07±1.69 dB with an average NF of only 2.8 dB over the 3~10 GHz band of interest, which is one of the best reported NF performances for a CMOS UWB DA or LNA in the literature. In addition, in low-gain (LG) mode, the 2×2 matrix DA consumed 6.86 mW and achieved S21 of 11.03±0.98 dB and an average NF of 4.25 dB over the 3~10 GHz band of interest, which is one of the best reported power dissipation (PD) performances for a CMOS UWB DA or LNA in the literature. A 2×3 matrix (two-stage) DA using the proposed dual-inductive-peaking cascade gain cell is demonstrated in 0.18 μm CMOS technology. It achieved S21 of 24.5±1.5 dB and an average NF of 3.9 dB over the frequency range of 0.3~10.5 GHz, which is one of the best reported S21 performances for a CMOS UWB DA in the literature. We improve the structure of 2×2 matrix to an optimal 1.2~8.6 GHz two-stage DA with cascade gain cell, which includes two enhanced CMOS inverters, using standard 0.18 μm CMOS technology. Multiple noise suppression techniques are used to achieve both flat and low NF and flat and high power gain (S21). In low-gain (LG) mode, the DA achieved S21 of 11.41±1.39 dB and an average NF of 3.74 dB for over frequencies of 1.2~8.6 GHz with a low power dissipation of 9.85 mW, which is the lowest power dissipation ever reported for a 0.18 μm CMOS DA or low-noise amplifier (LNA) with bandwidth wider than 6.5 GHz, S21 greater than 10 dB, and an average NF lower than 4 dB.
In the second half of this thesis, we demonstrate three low-power CMOS low noise amplifiers (LNAs) and two low-power receiver front-ends in the standard 0.18 μm CMOS technology. For the First LNA, a 2.76 mW 3~10 GHz common-gate (CG) LNA is demonstrated. Besides the 2.76 mW low power, we propose a new matching network (Instead of the traditional single parallel inductor (LS1 only)) and the compensated inductors (LC and LD2 are used to compensate the gain loss at medium-frequency and high-frequency, respectively) to enhance the bandwidth of input matching and S21, respectively. For the Second LNA, we improve the 2.76 mW CG LNA to a 0.99 mW 3~10 GHz CG CMOS UWB LNA, which is demonstrated by T-match input network and self-body-bias technique. At VG = 0.77 V, the LNA consumed 2.15 mW and achieved S11 of –10.4~ –35.5 dB, S21 of 10.4 dB, and an average NF of 4.9 dB over 3~10 GHz band of interest. At VG = 0.63 V, the LNA consumed 0.99 mW and achieved S11 of –10.7~ –35.8 dB, S21 of 7.9 dB and an average NF of 6 dB. These two are both the lowest PD ever reported for a UWB CMOS LNA with bandwidth greater than 6 GHz. For the third LNA, we improved the 2.76 mW CG LNA to a 3.2~9.7 GHz low-power LNA with high stop-band rejection filters (a passive and an active filters). The results show multiple rejection of 53.3/26.4/26.5/60/59.5 dB at 0.9/1.8/2.4/17.6/19.5 GHz, respectively. Besides the performances of PD of 4.68 mW, S21 of 10.8 dB, bandwidth of 6.5 GHz, and noise figure (NF) of 4.8 dB, the stop-band rejection was bigger than 21.6 dB between DC to 2.5 GHz and 11.2 to 20 GHz, respectively. A 3~9 GHz, 9.45 mW low-power, and 25.7±1.5 dB high gain receiver front-end with high stop-band rejection, which includes four finite transmission zeros, is demonstrated. In LG mode, this front-end only consumed 9.45 mW to achieve flat and high conversion gain of 25.7±1.5 dB, bandwidth of 6 GHz, NF of 6.95 dB, and input third-order intercept point (IIP3) of –8 dBm. The isolations of LO-RF/ LO-IF/ RF-IF were achieved by the proposed receiver front-end structure. The results were –91.9/ –42.7/ –67.1 dB and –95.6/ –37.9/ –65.9 dB in LG mode and in HG mode, respectively. These are the lowest power dissipation ever reported for a CMOS receiver front-end with conversion gain greater than 20 dB and bandwidth wider than or equal to 6 GHz in UWB (to the author's understanding). We improve the 9.45 mW low-power receiver front-end to an optimal variable gain low power CMOS UWB receiver front-end. The proposed receiver front-end consumed 7.2 mW and achieved conversion gain (CG) of 20.21±1.97 dB, minimum noise figure (NF) of 3.15 dB, and input third-order intercept point (IIP3) of –6 dBm. To the author’s knowledge, this is the lowest NF ever reported for a 0.18 μm CMOS UWB receiver front-end with power consumption lower than 10 mW.
The miniature 1.87 dB low-insertion-loss V-band bandpass filters with two finite transmission zeros are demonstrated in standard 0.13 μm CMOS technology. Over the frequency range of 49.5~82.5 GHz, this filter achieved insertion-loss (1/S21) lower than 3 dB, input return loss (S11), and output return loss (S22) better than –10 dB. The proposed filter architecture has the following feature: the low-frequency transmission-zero and high-frequency transmission-zero could be tuned by the series-feedback capacitor Cs and the parallel-feedback capacitor Cp, respectively. The chip area was only 0.466x0.307 mm2, i.e. 0.143 mm2, excluding the test pads.
Finally, a 60 GHz high performance (high power gain S21, saturation output power Psat, output 1 dB compression point P1dB, power added efficiency PAE) power amplifier with Wilkinson power divider/ combiner in TSMC 90 nm CMOS technology is demonstrated.

並列關鍵字

receiver front-end ； low-power ； low-noise ； distributed amplifier (DA) low-insertion-loss ； bandpass filter ； finite transmission zero ； power amplifier ； matrix ； low-noise Amplifier (LNA) ； V-band ； power added efficiency (PAE) ； Wilkinson power divider/ combiner ； transmission line (TL) inductor ； inductively-coupled plasma (ICP) etching ； gate terminal network ； group delay variation ； self-body-bias technique ； multiple stopband rejection ； saturation output power (Psat) ； output 1 dB compression point (P1dB)

參考文獻

[1] Ching-Piao Liang; Pei-Zong Rao; Tian-Jian Huang; Shyh-Jong Chung; “Analysis and Design of Two Low-Power Ultra-Wideband CMOS Low-Noise Amplifiers With Out-Band Rejection” IEEE Trans. on Microwave Theory and Techniques, vol. 58 , no. 2 ,2009

[2] Y. Gao, Y. J. Zheng, and B. L. Ooi, “0.18-um CMOS dual-band UWB LNA with interference rejection,” IET Electron. Lett., vol. 43, no. 20, pp. 1096–1098, Sep. 2007.

[3] T. O. Dickson, M. A. LaCroix, S. Boret, D. Gloria, R. Beekens, and S. P. Voinigescu, “30-100GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits” IEEE Tran. on Microwave Theory and Techniques, vol. 53, no.1, pp. 123-134, Jan. 2005.

[4] C. H. Doan, S. Emami, and A. M. Niknejad, “Millimeter-wave CMOS design,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, Jan. 2005, pp. 144-155.

[5] E. H. Westerwick, “A 5-GHz band CMOS low noise amplifier with a 2.5 dB noise figure,” 2001 International Symposium on VLSI-TSA Proc. of Tech. Papers, pp. 224-227.