晶片對晶片通訊之電容耦合互連技術的設計與實現

Design and Implementation of Capacitive Coupling Interconnect for Chip-to-Chip Communication

林綉蕙(Shiu-Hui Lin)

指導教授 ： 許孟烈

國立暨南國際大學/科技學院/電機工程學系/碩士(2007年)

https://doi.org/10.6837/NCNU.2007.00244

摘要

摘要

近年來積體電路製程技術進步，使得晶片內的工作速度增加，但是相較之下，晶片間的工作速度卻受限於封裝技術而增加有限，因此有一些取代傳統金屬連線的非直接接觸的連接方式被提出來，包含有光學式、無線射頻式和交流耦合式。而其中交流耦合式分為電感式耦合和電容式耦合，適合與標準CMOS製程整合。
本論文首先分析電容耦合傳輸通道的等效電路模型，並且分別以metal4和I/O pad 來做為耦合的電極板，以探討兩者所產生的耦合電容值(CC)和寄生電容值(CP)對傳輸效率的影響，實作晶片時則以晶片上內部耦合電容進行驗證，由實驗可得知當CC/CP比為1/8以上時，電容耦合資料傳輸可以正常工作。
吾人設計一電容耦合收發器晶片以進行實驗。在傳輸端利用鎖相迴路提供多相位時脈輸出給亂數產生器和4對1多工器，並將一組並列資料轉換為串列輸出，再經傳輸器使輸出的資料振幅放大，最後將資料傳輸至耦合的電極板上。耦合電容則透過晶片上耦合電容陣列的選取決定其耦合電容值，接收端以接收器接收耦合電極板上的耦合訊號，並將其回復為資料，所設計的電路採用國家晶片系統設計中心(CIC)提供的TSMC 3.3V 0.35μm 2P4M CMOS 製程實現，量測結果顯示傳輸端與接收器的工作速度可達到1Gbps。

關鍵字

電容耦合 ； 互連技術 ； 收發器

並列摘要

Abstract
As the integrated circuit fabrication technology advances, on-chip operating speed is increased substantially but the off-chip operating speed is limited by the package. Therefore, several non-direct contact technologies such as optical, RF and AC-coupled, have been proposed to replace traditional metal wire interconnect. The AC-coupled technologies which include inductive coupling and capacitive coupling can be suitably integrated with standard CMOS process.
In this work, the equivalent circuit model of data transfer channel of capacitive coupling has been analyzed. The influence of the coupling and parasitic capacitances on transfer efficiency has been explored by using metal4 and I/O pad to fabricate coupled capacitor plates, respectively. The capacitive coupling interconnect works properly when the CC/CP ratio is greater than 1/8, which has been proved by on-chip coupled capacitance.
An experimental capacitive coupling transceiver was designed. The transmitter uses a phase locked loop to provide multi-phase clocks for PRBS circuit and 4-to-1 multiplexer to convert parallel data into serial one. The transmitter drives data to a coupled capacitor selected from an on-chip capacitor array. The receiver picks up coupled signal from the coupled capacitor plate and recovers the data. The circuit is implemented in TSMC 3.3V 0.35µm 2P4M CMOS process provided by Chip Implementation Center (CIC). The simulation and measurement results show that the chip can operate functionally at 1 Gbps

並列關鍵字

Capacitive Coupling ； Interconnect ； Transceiver

參考文獻

參考文獻

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University Press, 2004.