晶片設計封裝及電路板共同設計方法

在現今的積體電路設計流程中，晶片、封裝、以及電路板三個領域的設計經常是分開的。在如此的設計流程之下，各設計團隊無法獲得其他領域的資訊，而使得設計出來的結果往往在要在結合時產生相當大的困難。尤其晶片及封裝在設計時往往沒有考慮電路板上的繞線問題，導致電路板上的繞線無法完成或是品質降低，如此一來必須回頭重新設計晶片及封裝。一般的設計往往都要經過好幾次這樣回頭重新設計的過程，造成整個設計流程的瓶頸，使得上市時間受到拖延，產品的獲利也會下降。在本論文中，我們對於覆晶封裝重分配層繞線以及印刷電路板逃脫繞線的現存文獻進行了廣泛的調查及整理，將他們的方法進行有系統地介紹，並詳細分析與評估其優缺點。接著，本論文提出一個晶片設計封裝及電路板共同設計流程，在晶片及覆晶封裝設計時即可將電路板上之繞線納入考慮之內。此共同設計流程包含以下關鍵步驟：(1)反向逃脫繞線，以決定電路板上球柵陣列之訊號分配；(2)考慮封裝之晶片擺置，將輸入輸出緩衝器擺置在有利於重分配層繞線之位置；(3) 重分配層中凸塊接點之訊號重新指定，同時考慮重分配層及電路板上之繞線擁塞情況並將兩層平衡；(4)重分配層繞線及電路板球柵陣列之逃脫繞線，將繞線完成。實驗中將本共同設計流程和傳統設計流程以及兩個其他考慮電路板之設計流程比較，對所有的測試資料皆只有本共同設計流程能夠成功地同時完成重分配層繞線及印刷電路板逃脫繞線，結果顯示本論文提出之共同設計流程效果顯著。

關鍵字

實體設計；共同設計；覆晶繞線；逃脫繞線；晶片擺置

並列摘要

In today's IC production, the design processes of chip, package, and board are separate from each other. However, the lack of information from other domains dramatically increases the design difficulty and reduces the quality of the product. Especially, while most current IC's still resides on a Printed Circuit Board (PCB), the PCB is usually not considered during the design of chip and package, which makes the PCB routing very difficult to complete with satisfying quality. As a result, PCB routing often becomes the bottleneck of the whole design flow, which significantly lengthens the time to market and reduces the profit margin. In this thesis, we provide an extensive survey about the previous works on flip-chip RDL routing and PCB escape routing. We systematically introduce the methods and analyze their strengths and weaknesses in detail. After that, we propose a chip-package-board codesign methodology that provides cross-domain information integration. Our codesign flow has four major procedures: (1) inverse escape routing for board signal-ball assignment, (2) package aware I/O placement that reduces the RDL routing congestion, (3) RDL bump reassignment that balances the routing congestion of RDL and board, and (4) RDL and escape routing that completes the flow. Experimental results show that our codesign flow successfully complete the routing for all test cases while the traditional flow and other two board-driven flows all fail at either RDL routing or PCB escape routing.

並列關鍵字

physical design ； chip-package-board codesign ； flip-chip routing ； escape routing ； chip placement

參考文獻

[1] Ravindra K. Ahuja, Thomas L. Magnanti, and James B. Orlin. Network Flows: Theory, Algorithms, and Applications. Prentice Hall, 1993.

[2] Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, and Yao-Wen Chang, NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 27(7):1228 1240,

[3] Thomas H. Cormen, Charles E. Leiserson, Ronald L. Rivest, and Cli ord Stein. Introduction to Algorithms. The MIT Press, 2009.

co-design considering signal skews, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(5):711 721, 2010.

[6] Jia-Wei Fang, Kuan-Hsien Ho, and Yao-Wen Chang, Routing for chip-package-board co-design considering di erential pairs, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 512 517, 2008.

國際替代計量

晶片設計封裝及電路板共同設計方法

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