基於延遲鎖定迴路之全數位可程式化頻率合成器設計

Design of an All-Digital Programmable DLL-Based Frequency Synthesizer

魏仕穠(Shih-Nung Wei)

指導教授 ： 王義明

國立暨南國際大學/科技學院/電機工程學系/碩士(2010年)

摘要

隨著製程技術的演進，積體電路朝向高密度與高整合度的系統單晶片(System-on-a-Chip, SoC)發展，而晶片中各模組的時脈產生與同步問題也日益複雜與重要，甚至成為高效能系統的發展瓶頸之一。
近年來，延遲鎖定迴路(Delay-locked Loop, DLL)被應用於系統時脈產生器中。相較於傳統鎖相迴路式的系統時脈產生器(PLL-based system clock generator)，延遲鎖定迴路式的系統時脈產生器(DLL-based system clock generator)架構上不會有時脈抖動累積的問題，故其具有低抖動與低相位雜訊的特點。根據研究結果顯示，延遲鎖定迴路式的系統時脈產生器將更適合於高性能或高速的系統單晶片使用，以確保整體運作的強健性。
傳統延遲鎖定迴路式的系統時脈產生器使用循環式延遲線(Cyclic Delay Line)或邊緣合成器來達到可程式化倍頻的功能。但是其存在下列問題：
1. 時脈訊號循環在延遲線迴圈中，導致時脈抖動累積。
2. 邊緣合成器藉由選擇多工器的不同輸入訊號來達到倍頻功能，卻造成時脈訊號工作週期與頻率變異。
本論文提出一個新型全數位延遲鎖定迴路式的頻率合成器。在架構設計上使用數位至時間維度轉換器(Digital to Time-domain Converter, DTC)與唯讀記憶體(ROM)取代傳統的邊緣合成器，其架構特點如下：
1. 回授路徑中無需使用多工器，故輸出工作週期與頻率變異更小。
2. 縱使外部輸入訊號工作週期不為50%，其合成頻率輸出之工作週期皆為50%。
3. 藉由規劃唯讀記憶體的內容，即可達到任意倍頻數輸出。(本論文實現的倍頻包含：1x、2x、4/3x、4x、1/3x、2/3x與1/2x)
4. 具有相位調整與鎖定功能，可同時產生同相位的倍頻系統時脈。
在TSMC 0.18-μm 1P6M CMOS製程與電源電壓1.8V的設計條件下，HSPICE電路模擬結果顯示當電路輸入訊號頻率範圍為25MHz-650MHz，其輸出訊號頻率範圍為8.333MHz-2.6GHz且輸出訊號工作週期變異範圍為50±2%；當輸入訊號頻率範圍在400MHz-650MHz下，輸出訊號與輸入訊號相位誤差可校正達到19ps內。當輸出訊號頻率為2.6GHz時，功率消耗為12.04mW。

關鍵字

系統單晶片 ； 延遲鎖定迴路 ； 頻率合成器 ； 數位至時間維度轉換器

並列摘要

With the evolution of process technology, the development of the integrated circuit has moved toward a high-density and high-integrated System-on-a-Chip (SoC). The clock generation and synchronization issues among different modules on SoC become more complex and important, and even turn into one of the bottlenecks in high performance systems.
In recent years, the Delay-locked loop (DLL) is used in system clock generators. Compared with conventional PLL-based system clock generators, DLL-based system clock generators exhibit less jitter and phase noise because of no jitter accumulation phenomenon in nature. According to the related research results, the DLL-based system clock generator is much more suitable for high-performance and/or high-speed SOCs to ensure the robustness of the entire system.
The cyclic delay line or edge combiner is adapted in conventional DLL-based system clock generators to achieve the function of programmable frequency multiplication. However, these circuits result in several problems listing as follows.
1. The clock signal cycles in delay-line loop causing jitter accumulation.
2. By selecting different input signal of multiplexer, the edge combiner can produce multiplied frequency output. Nevertheless, in feedback loop the latency of multiplexer causes the variations of duty-cycle and frequency of output clock.
In this thesis, a novel all-digital DLL-based frequency synthesizer (AD-DFS) was proposed. In the architecture design, digital to time-domain converter (DTC) and read-only memory (ROM) are used to replace the edge combiner in conventional DLL-based frequency synthesizer. With this novel architecture, several gains are shown below.
1. The multiplexer is no longer required in feedback path. Hence, the variations of output duty-cycle and frequency will become less.
2. Even the input clock duty-cycle is not 50%, the duty-cycle of the synthesized output clock will be very close to 50%.
3. By programming the content of read-only memory, arbitrary multiplication ratio can be realized. (In this thesis, the implemented multiplication ratios include 1x, 2x, 4/3x, 4x, 1/3x, 2/3x, and 1/2x)
4. The phase adjustment and tracking function are also merged into the architecture design, so that the output clock not only has a synthesized frequency but also in phase with input clock.
When designed with a 0.18 μm CMOS 1.8 V process technology, HSPICE simulation results show that the output frequency of the proposed AD-DFS ranges from 8.33 MHz to 2.6 GHz the output duty-cycle has an only 2% deviation. Besides, when the proposed AD-DFS operates from 400 MHz to 650 MHz, the static phase error between the input clock and output clock will be kept less than 19 ps. Furthermore, the maximal power consumption is 12.04 mW at output frequency 2.6 GHz.

並列關鍵字

SoC ； delay-locked loop ； frequency synthesizer ； digital to time-domain converter

參考文獻

參考文獻

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