新的全數位頻率與相位合成器設計與分析

Design and Analysis of Novel All-Digital Frequency and Phase Synthesizer

張智鈞(Chih-Chun Chang)

指導教授 ： 趙燿庚

元智大學/工程學院/通訊工程學系/碩士(2005年)

摘要

本論文是以Hugh Mair及Liming Xiu所提出之全數位頻率與相位合成器架構(All-Digital PLL)為基礎來做改良設計，此架構是以多個壓控振盪器輸出的相同頻率及相同相位差的訊號，做為DCO(flying-adder architecture)的內部輸出訊號，再以控制位元(control word)決定出所欲同步訊號。而控制位元中包含了整數與小數部分位元，故可決定出一定頻率範圍內的任何頻率的同步訊號。
而改良型架構主要是修改了DCO(flying-adder architecture)的部分內部電路，以期能提昇可同步訊號的頻率範圍，以及減少使用壓控振盪器輸出訊號的個數，進而降低耗電量。最後再以Modelsim軟體模擬的結果，來驗證與比較改良型架構的效益。

關鍵字

全數位頻率與相位合成器

並列摘要

The thesis is based on the architecture of All-Digital Frequency and Phase Synthesizer (All-Digital PLL) which is published by Hugh Mair and Liming Xiu. The architecture makes multiple signals of the same frequency and the same phase difference the output of a voltage-control-oscillator to be the internal input of the DCO (flying-adder architecture), and we utilize the control word to decide the desired synchronized output signal. However, the control
word consists of a integral part and a fractional part, so it can decide the signal of any frequency in certain frequency range.
The main modification of the modified architecture is in the internal circuit of the DCO (flying-adder architecture), we hope it can raise the frequency range of the synchronized signal, and reduce the number of the output signal of a voltage-control-oscillator, and then we can decrease the power consumption. Lastly, we utilizethe Modelsim to simulate the performance of architecture for proving and comparing the benefit with the modified architecture.

並列關鍵字

Frequency Synthesizer

參考文獻

[1] H. Mair and L. Xiu, “An architecture of high performance frequency and phase synthesis,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 835-864, Jun. 2000.

[2] L. Xiu and Z. You, “An flying-adder architecture of frequency and phase synthesis with scalability,” IEEE Trans. Very Large Scale Integrat. (VLSI) Syst., vol. 10, no. 5, pp. 637-649, Oct. 2002.

[4] L. Xiu, W. Li, J. Meiners, and R. Padakanti, “A novel all-digital PLL with software adaptive filter,” IEEE J. Solid-State Circuits, vol. 39, no. 3, pp. 476-483, Mar. 2004.

[5] L. Xiu and Z. You, “A flying-adder frequency synthesis architecture of reducing VCO stages,” IEEE Tran. On very large scale integration (VLSI) systems, vol. 13, no. 2, Feb. 2005.

[7] William C. Lindsey and Chak Ming Chie, “A Survey of Digital Phase-Locked Loops,” proceedings of the IEEE, vol. 69, NO. 4 April 1981.