數位控制寬範圍頻率合成器之設計

Design of Digital Control Wide Range Frequency Synthesizer

林貝儒(Pei-Ju Lin)

指導教授 ： 黃育賢 ； 陳建中

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2006年)

摘要

對現代通訊系統而言，一個精準的頻率是不可或缺的元件，不論是光通訊或是無線通訊，訊號的調變都需要一個精準的訊號源。鎖相迴路技術已發展多年且是最常應用於實現一個訊號源，本論文著重於寬範圍鎖相迴路及頻率合成器設計，電路包含相位頻率偵測器(Phase Frequency Detector)、電荷充放器(Charge Pump)、迴路濾波器(Loop Filter)、壓控振盪器(Voltage Controlled Oscillator)與除頻器(Frequency Divider)的部份。
相位頻率偵測器可偵測兩訊號相位差，產生足夠寬度的充放電脈衝訊號，供給電荷充放器產生控制電壓，使用之電荷充放器電路具有電流匹配特性且不再具有啟動階段(start-up)問題，可以有效的抑制雜訊的產生，迴路濾波器採用二階RC電路組成，可濾除電荷充放器的高頻成份，壓控振盪器其數位控制接腳選擇需要的頻率，整個電路的組合可提供快速調整、精確、且寬頻的頻率合成器。
提出的寬範圍頻率合成器採用TSMC 0.35μm 2P4M CMOS製程，電源電壓3.3V，應用頻率範圍可操作輸入頻率在10MHz~100MHz，輸出頻率為100MHz ~600MHz，功率損耗為6.8463 mW，佈局總面積為1.2 × 1.2mm2。

關鍵字

鎖相迴路 ； 電荷充放器 ； 壓控振盪器 ； 頻率合成器

並列摘要

For a modern communication system, a precise frequency is necessary. The PLL (phase-locked loop) technique has been developed for many years. This dissertation focuses on the design of wide range PLL and frequency synthesizer. The proposed circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider.
The PFD can detect the difference of two signals and generate a wide charge or discharge pulse signal for the charge pump to generate a controlling voltage. It will be no more start-up problem when we use the charge pump with matched current and make the complete circuit can depress the generation of noise efficiently. The loop filter is composed by a second-order RC circuit and is capable to filtrate the high frequency part of the charge pump. The VCO provide the digital controlling selections of frequency. The whole circuit provides a fast tune, accurate, and wide range frequency synthesizer.
The proposed wide range frequency synthesizer was designed in TSMC 0.35um CMOS process with supply voltage 3.3V. The applied frequency range is able to operate in 10MHz~100MHz for the input frequency and 100MHz ~ 600MHz for the output frequency. The power consumption is 6.8463mW. The total layout area is 1.2 * 1.2mm2.

並列關鍵字

Phase-Locked Loop ； Charge Pump ； Voltage Controlled Oscillator ； Frequency Synthesizer

參考文獻

[18]王三輔, 無死區效應之資料鎖相迴路與頻率合成器的新架構設計, 碩士論文 國立臺北科技大學電腦通訊與控制研究所, 台北, 2005.

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